M29DW128G70NF6E NUMONYX, M29DW128G70NF6E Datasheet - Page 8



Manufacturer Part Number
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The M29DW128G is a 128-Mbit (8 Mbit x16) non-volatile memory that can be read, erased
and reprogrammed. These operations can be performed using a single low voltage (2.7 to
3.6 V) supply. At power-up the memory defaults to its read mode.
The M29DW128G features an asymmetrical block architecture, with 8 parameter and 62
main blocks, divided into four banks, A, B, C and D, providing multiple bank operations.
While programming or erasing in one bank, read operations are possible in any other bank.
The bank architecture is summarized in
of the memory address space, and four are at the bottom.
Program and erase commands are written to the command interface of the memory. An on-
chip program/erase controller simplifies the process of programming or erasing the memory
by taking care of all of the special operations that are required to update the memory
contents. The end of a program or erase operation can be detected and any error conditions
identified. The command set required to control the memory is consistent with JEDEC
The Chip Enable, Output Enable and Write Enable signals control the bus operations of the
memory. They allow simple connection to most microprocessors, often without additional
The device supports asynchronous random read and page read from all blocks of the
memory array. The device also features a write to buffer program capability that improves
the programming throughput by programming in one shot a buffer of 32 words. The
enhanced buffered program feature is also available to speed up the programming
throughput, allowing to program 256 words in one shot. The V
enable faster programming of the device.
The M29DW128G has one extra 256 words block (extended block, 128 words factory locked
and 128 words customer lockable) that can be accessed using a dedicated command. The
extended block can be protected and so is useful for storing security information. However
the protection is irreversible, once protected the protection cannot be undone.
Each block can be erased independently, so it is possible to preserve valid data while old
data is erased.
The device features different levels of hardware and software block protection to avoid
unwanted program or erase (modify):
The memory is offered in TSOP56 (14 x 20 mm) and TBGA64 (10 x 13 mm, 1 mm pitch)
packages. The memory is delivered with all the bits erased (set to ‘1’).
Hardware protection
Software protection
Additional protection features are available upon customer request.
The V
blocks (two at the top and two at the bottom of the address space)
Volatile protection
Non-volatile protection
Password protection
/WP provides a hardware protection of the four outermost parameter
2. Four of the parameter blocks are at the top
/WP signal can be used to

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