ATTINY12L-4PU Atmel, ATTINY12L-4PU Datasheet

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... Packages – 8-pin PDIP and SOIC • Operating Voltages – 1.8 - 5.5V for ATtiny12V-1 – 2.7 - 5.5V for ATtiny11L-2 and ATtiny12L-4 – 4.0 - 5.5V for ATtiny11-6 and ATtiny12-8 • Speed Grades – 1.2 MHz (ATtiny12V-1) – MHz (ATtiny11L-2) – MHz (ATtiny12L-4) – ...

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... CISC microcontrollers. Table 1. Parts Description Device Flash EEPROM ATtiny11L 1K - ATtiny11 1K - ATtiny12V ATtiny12L ATtiny12 The ATtiny11/12 AVR is supported with a full suite of program and system development tools including: macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. Register Voltage Range Frequency 32 2.7 - 5.5V ...

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... The device is manufactured using Atmel’s high-density nonvolatile memory technology. By combining an RISC 8-bit CPU with Flash on a monolithic chip, the Atmel ATtiny11 is a powerful microcontroller that provides a highly-flexible and cost-effective solution to many embedded control applications. ...

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... The device is manufactured using Atmel’s high-density nonvolatile memory technology. By combining an RISC 8-bit CPU with Flash on a monolithic chip, the Atmel ATtiny12 is a powerful microcontroller that provides a highly-flexible and cost-effective solution to many embedded control applications. ...

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Pin Descriptions VCC GND Port B (PB5..PB0) XTAL1 XTAL2 RESET 1006F–AVR–06/07 Supply voltage pin. Ground pin. Port 6-bit I/O port. PB4..0 are I/O pins that can provide internal pull-ups (selected for each bit). On ATtiny11, PB5 is ...

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Architectural Overview ATtiny11/12 6 The fast-access register file concept contains 32 x 8-bit general-purpose working regis- ters with a single-clock-cycle access time. This means that during one single clock cycle, one ALU (Arithmetic Logic Unit) operation is executed. Two operands ...

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ALU – Arithmetic Logic Unit Subroutine and Interrupt Hardware Stack 1006F–AVR–06/07 Figure 3. The ATtiny11/12 AVR RISC Architecture 8-bit Data Bus Program 512 x 16 Counter Program Flash Instruction Register Direct Addressing Instruction Decoder Control Lines A flexible interrupt module ...

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General-purpose Register File ATtiny11/12 8 Figure 4 shows the structure of the 32 general-purpose registers in the CPU. Figure 4. AVR CPU General-purpose Working Registers 7 General- purpose Working Registers R30 (Z-register low byte) R31 (Z-register high byte) All the ...

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Status Register Status Register – SREG 1006F–AVR–06/07 The AVR status register (SREG) at I/O space location $3F is defined as: Bit $ Read/Write R/W R/W R/W Initial Value • Bit 7 ...

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System Clock and Clock Options Internal RC Oscillator ATtiny12 Calibrated Internal RC Oscillator Crystal Oscillator ATtiny11/12 10 The device has the following clock source options, selectable by Flash fuse bits as shown: Table 3. Device Clocking Options Select Device Clocking ...

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External Clock External RC Oscillator 1006F–AVR–06/07 To drive the device from an external clock source, XTAL1 should be driven as shown in Figure 6. Figure 6. External Clock Drive Configuration EXTERNAL OSCILLATOR SIGNAL For timing insensitive applications, the external RC ...

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Register Description Oscillator Calibration Register – OSCCAL ATtiny11/12 12 Bit $31 CAL7 CAL6 CAL5 Read/Write R/W R/W R/W Initial Value • Bits 7..0 - CAL7..0: Oscillator Calibration Value Writing the calibration byte to this ...

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Memories I/O Memory Program and Data Addressing Modes 1006F–AVR–06/07 The I/O space definition of the ATtiny11/12 is shown in the following table: Table 5. ATtiny11/12 I/O Space Address Hex Name Device $3F SREG ATtiny11/12 $3B GIMSK ATtiny11/12 $3A GIFR ATtiny11/12 ...

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Register Direct, Single Register Rd Register Indirect Register Direct, Two Registers Rd and Rr ATtiny11/12 14 Figure 8. Direct Single-register Addressing The operand is contained in register d (Rd). Figure 9. Indirect Register Addressing The register accessed is the one ...

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I/O Direct Relative Program Addressing, RJMP and RCALL Constant Addressing Using the LPM Instruction 1006F–AVR–06/07 Figure 11. I/O Direct Addressing Operand address is contained in 6 bits of the instruction word the destination or source register address. Figure ...

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Memory Access and Instruction Execution Timing ATtiny11/12 16 This section describes the general access timing concepts for instruction execution and internal memory access. The AVR CPU is driven by the System Clock Ø, directly generated from the external clock crystal ...

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Flash Program Memory EEPROM Data Memory Prevent EEPROM Corruption ATtiny12 EEPROM Read/Write Access 1006F–AVR–06/07 The ATtiny11/12 contains 1K bytes on-chip Flash memory for program storage. Since all instructions are single 16-bit words, the Flash is organized as 512 x 16 ...

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Register Description EEPROM Address Register – EEAR EEPROM Data Register – EEDR EEPROM Control Register – EECR ATtiny11/12 18 Bit $ EEAR5 Read/Write R R R/W Initial Value The EEPROM Address Register ...

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EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 2 and 3 is unessential): 1. Wait until EEWE becomes zero. 2. Write new EEPROM address to EEAR (optional). ...

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Sleep Modes Sleep Modes for the ATtiny11 Idle Mode Power-down Mode Sleep Modes for the ATtiny12 Idle Mode Power-down Mode ATtiny11/ enter the sleep modes, the SE bit in MCUCR must be set (one) and a SLEEP instruc- ...

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MCU. Note that if a level triggered or pin change interrupt is used for wake-up from Power- down Mode, the changed level ...

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System Control and Reset Reset Sources ATtiny11/12 22 The ATtiny11/12 provides three or four sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the power-on reset threshold (V ). POT • External Reset. ...

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Power-on Reset for the ATtiny11 1006F–AVR–06/07 A Power-on Reset (POR) circuit ensures that the device is reset from power-on. As shown in Figure 15, an internal timer is clocked from the watchdog timer. This timer pre- vents the MCU from ...

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ATtiny11/12 24 Figure 16. Reset Logic for the ATtiny12 Power-on Reset Circuit Brown-out BODEN Reset Circuit BODLEVEL On-chip RC Oscillator Table 9. Reset Characteristics for the ATtiny12 Symbol Parameter Power-on Reset Threshold Voltage (rising) (1) V POT Power-on Reset Threshold ...

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Table 10. ATtiny12 Clock Options and Start-up Times CKSEL3..0 Clock Source 1111 Ext. Crystal/Ceramic Resonator 1110 Ext. Crystal/Ceramic Resonator 1101 Ext. Crystal/Ceramic Resonator 1100 Ext. Crystal/Ceramic Resonator 1011 Ext. Crystal/Ceramic Resonator 1010 Ext. Crystal/Ceramic Resonator 1001 Ext. Low-frequency Crystal ...

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Power-on Reset for the ATtiny12 ATtiny11/ Power-on Reset (POR) pulse is generated by an on-chip detection circuit. The detec- tion level is nominally 1.4V. The POR is activated whenever V level. The POR circuit can be used to ...

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External Reset Brown-out Detection (ATtiny12) 1006F–AVR–06/07 An external reset is generated by a low level on the RESET pin. Reset pulses longer than 50 ns will generate a reset, even if the clock is not running. Shorter pulses are not ...

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Watchdog Reset Register Description MCU Status Register – MCUSR of the ATtiny11 ATtiny11/12 28 When the Watchdog times out, it will generate a short reset pulse cycle dura- tion. On the falling edge of this pulse, the ...

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MCU Status Register – MCUSR for the ATtiny12 1006F–AVR–06/07 To identify a reset condition, the user software should clear both the PORF and EXTRF bits as early as possible in the program. Checking the PORF and EXTRF values is done ...

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Interrupts Reset and Interrupt ATtiny11/12 30 The ATtiny11 provides four different interrupt sources and the ATtiny12 provides five. These interrupts and the separate reset vector each have a separate program vector in the program memory space. All the interrupts are ...

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Interrupt Handling Interrupt Response Time External Interrupt 1006F–AVR–06/07 $004 rjmp $005 rjmp ; $006 MAIN: <instr> … … … The ATtiny11/12 has two 8-bit Interrupt Mask control registers; GIMSK – General Inter- rupt Mask register and TIMSK – Timer/Counter Interrupt ...

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Pin Change Interrupt Register Description MCU Control Register – MCUCR ATtiny11/12 32 The pin change interrupt is triggered by any change on any input or I/O pin. Change on pins PB2..0 will always cause an interrupt. Change on pins PB5..3 ...

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General Interrupt Mask Register – GIMSK 1006F–AVR–06/07 • Bits ISC01, ISC00: Interrupt Sense Control0 Bit 1 and Bit 0 The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding ...

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General Interrupt Flag Register – GIFR Timer/Counter Interrupt Mask Register – TIMSK ATtiny11/12 34 Bit $3A - INTF0 PCIF Read/Write R R/W R/W Initial Value • Bit 7 - Res: Reserved Bit This bit ...

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Timer/Counter Interrupt Flag Register – TIFR 1006F–AVR–06/07 Bit Read/Write R R Initial Value 0 0 • Bits 7..2 - Res: Reserved Bits These bits are reserved bits in the ATtiny11/12 and always read as zero. ...

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I/O Port B ATtiny11/12 36 All AVR ports have true read-modify-write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintention- ally changing the direction of any other ...

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Register Description Port B Data Register – PORTB Port B Data Direction Register – DDRB Port B Input Pins Address – PINB Port B as General Digital I/O 1006F–AVR–06/07 Bit $ Read/Write R R ...

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Alternate Functions of Port B ATtiny11/12 38 All port B pins are connected to a pin change detector that can trigger the pin change interrupt. See “Pin Change Interrupt” on page 32 for details. In addition, Port B has the ...

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Timer/Counter0 Timer/Counter Prescaler 1006F–AVR–06/07 The ATtiny11/12 provides one general-purpose 8-bit Timer/Counter – Timer/Counter0. The Timer/Counter0 has prescaling selection from the 10-bit prescaling timer. The Timer/Counter0 can either be used as a timer with an internal clock timebase ...

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ATtiny11/12 40 Figure 23. Timer/Counter0 Block Diagram T0 1006F–AVR–06/07 ...

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Register Description Timer/Counter0 Control Register – TCCR0 Timer Counter 0 – TCNT0 1006F–AVR–06/07 Bit $ Read/Write Initial Value • Bits 7..3 - Res: Reserved Bits These bits are ...

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Timer/Counter Interrupt Mask Register – TIMSK Timer/Counter Interrupt Flag Register – TIFR ATtiny11/12 42 Bit $ Read/Write Initial Value • Bit 7..2 - Res: Reserved Bits These bits ...

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Watchdog Timer Register Description Watchdog Timer Control Register – WDTCR 1006F–AVR–06/07 The Watchdog Timer is clocked from a separate on-chip oscillator. By controlling the Watchdog Timer prescaler, the Watchdog reset interval can be adjusted as shown in Table 19. See ...

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ATtiny11/ the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four ...

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Analog Comparator Register Description Analog Comparator Control and Status Register – ACSR 1006F–AVR–06/07 The Analog Comparator compares the input values on the positive input PB0 (AIN0) and negative input PB1 (AIN1). When the voltage on the positive input PB0 (AIN0) ...

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ATtiny11/12 46 • Bit 4 - ACI: Analog Comparator Interrupt Flag This bit is set (one) when a comparator output event triggers the interrupt mode defined by ACI1 and ACI0. The Analog Comparator Interrupt routine is executed if the ACIE ...

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ATtiny12 Internal Voltage Reference Voltage Reference Enable Signals and Start-up Time 1006F–AVR–06/07 ATtiny12 features an internal voltage reference with a nominal voltage of 1.22V. This reference is used for Brown-out Detection, and it can be used as an input to ...

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Memory Programming Program (and Data) Memory Lock Bits Fuse Bits in ATtiny11 Fuse Bits in ATtiny12 ATtiny11/12 48 The ATtiny11/12 MCU provides two lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional ...

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... PB5 while the ATtiny12 is in Power-on Reset. If not, the part can fail to enter programming mode caused by drive contention on PB0 and/or PB5. All Atmel microcontrollers have a three-byte signature code which identifies the device. The three bytes reside in a separate address space. ...

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... Low-voltage Serial Programming ATtiny11L Not applicable ATtiny11 Not applicable ATtiny12V 2.2 - 5.5V ATtiny12L 2.7 - 5.5V ATtiny12 4.0 - 5.5V This section describes how to program and verify Flash Program memory, EEPROM Data memory (ATtiny12), lock bits and fuse bits in the ATtiny11/12. Figure 26. High-voltage Serial Programming 11 ...

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High-voltage Serial Programming Algorithm 1006F–AVR–06/07 To program and verify the ATtiny11/12 in the High-voltage Serial Programming mode, the following sequence is recommended (See instruction formats in Table 23): 1. Power-up sequence: Apply 4.5 - 5.5V between V to “0” and ...

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Figure 27. High-voltage Serial Programming Waveforms SERIAL DATA INPUT PB0 SERIAL INSTR. INPUT PB1 SERIAL DATA OUTPUT MSB PB2 SERIAL CLOCK INPUT 0 XTAL1/PB3 Table 23. High-voltage Serial Programming Instruction Set for ATtiny11/12 Instruction Instr.1 PB0 0_1000_0000_00 Chip Erase PB1 ...

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Table 23. High-voltage Serial Programming Instruction Set for ATtiny11/12 (Continued) Instruction Instr.1 PB0 0_0000_0000_00 Read EEPROM PB1 0_0110_1000_00 byte (ATtiny12) PB2 x_xxxx_xxxx_xx PB0 0_0100_0000_00 Write Fuse bits PB1 0_0100_1100_00 (ATtiny11) PB2 x_xxxx_xxxx_xx PB0 0_0100_0000_00 Write Fuse bits PB1 0_0100_1100_00 (ATtiny12) ...

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High-voltage Serial Programming Characteristics Low-voltage Serial Downloading (ATtiny12 only) ATtiny11/12 54 Figure 28. High-voltage Serial Programming Timing SDI (PB0), SII (PB1) SCI (PB3) SDO (PB2) Table 24. High-voltage Serial Programming Characteristics T 5.0V ± 10% (Unless otherwise noted) Symbol Parameter ...

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Low-voltage Serial Programming Algorithm 1006F–AVR–06/07 If the chip Erase command in Low-voltage Serial Programming is executed only once, one data byte may be written to the flash after erase. Using the following algorithm guar- antees that the flash will be ...

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Data Polling ATtiny11/12 56 next instruction. See Table 28 on page 58 for t an erased device, no $FFs in the data file(s) needs to be programmed. 6. Any memory location can be verified by using the Read instruction which ...

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Table 25. Low-voltage Serial Programming Instruction Set Instruction Byte 1 1010 1100 Programming Enable 1010 1100 Chip Erase 0010 H000 Read Program Memory 0100 H000 Write Program Memory Read EEPROM 1010 0000 Memory Write EEPROM 1100 0000 Memory 1010 1100 ...

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Low-voltage Serial Programming Characteristics ATtiny11/12 58 Figure 31. Low-voltage Serial Programming Timing MOSI t OVSH SCK MISO Table 26. Low-voltage Serial Programming Characteristics 2.2 - 5.5V (Unless otherwise noted) CC Symbol Parameter 1/t Oscillator Frequency (V CLCL ...

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Electrical Characteristics Absolute Maximum Ratings Operating Temperature.................................. -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-1. Voltage on RESET with respect to Ground......-1.0V to +13.0V Maximum Operating ...

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... CC (ATtiny11L) Active 4 MHz (ATtiny12L) Active 6 MHz (ATtiny11) Active 8 MHz (ATtiny12) Idle 1 MHz (ATtiny12V) Idle 2 MHz (ATtiny11L) Idle 4 MHz (ATtiny12L) Idle 6 MHz (ATtiny11) Idle 8 MHz (ATtiny12) (5) Power Down , V = 3V, CC WDT enabled (5) Power Down , V = 3V. CC WDT disabled (ATtiny12) (5) Power Down , V = 3V. CC WDT disabled (ATtiny11) ...

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External Clock Drive Waveforms 1006F–AVR–06/07 Figure 32. External Clock VIH1 VIL1 External Clock Drive ATtiny11 Symbol Parameter 1/t Oscillator Frequency CLCL t Clock Period CLCL t High Time CHCX t Low Time CLCX t Rise Time CLCH t Fall Time ...

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ATtiny11 Typical Characteristics ATtiny11/12 62 The following charts show typical behavior. These figures are not tested during manu- facturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave ...

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Figure 34. Active Supply Current vs. V ACTIVE SUPPLY CURRENT vs 2.5 3 Figure 35. Active Supply Current vs. V ACTIVE SUPPLY CURRENT vs. V DEVICE ...

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ATtiny11/12 64 Figure 36. Active Supply Current vs. V ACTIVE SUPPLY CURRENT vs. V DEVICE CLOCKED BY 32KHz CRYSTAL 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 2.5 3 3.5 Figure 37. Idle Supply Current vs. Frequency ...

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Figure 38. Idle Supply Current vs. V IDLE SUPPLY CURRENT vs 2.5 3 Figure 39. Idle Supply Current vs. V IDLE SUPPLY CURRENT vs. V DEVICE CLOCKED BY 1.0MHz INTERNAL RC ...

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ATtiny11/12 66 Figure 40. Idle Supply Current vs. V IDLE SUPPLY CURRENT vs. V DEVICE CLOCKED BY 32KHz CRYSTAL 2.5 3 3.5 Figure 41. Power-down Supply Current vs. V POWER-DOWN SUPPLY CURRENT vs. V ...

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Figure 42. Power-down Supply Current vs. V POWER-DOWN SUPPLY CURRENT vs. V WATCHDOG TIMER ENABLED 1.5 2 2.5 3 Figure 43. Analog Comparator Current vs. V ANALOG COMPARATOR CURRENT ...

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ATtiny11/12 68 Analog comparator offset voltage is measured as absolute offset. Figure 44. Analog Comparator Offset Voltage vs. Common Mode Voltage ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE ...

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Figure 46. Analog Comparator Input Leakage Current ANALOG COMPARATOR INPUT LEAKAGE CURRENT -10 0 0.5 1 1.5 2 2.5 Figure 47. Watchdog Oscillator Frequency vs. V WATCHDOG OSCILLATOR FREQUENCY vs. V 1600 ...

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ATtiny11/12 70 Sink and source capabilities of I/O ports are measured on one pin at a time. Figure 48. Pull-up Resistor Current vs. Input Voltage PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE 120 ˚ A 100 T ...

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Figure 50. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE ˚ ˚ 0.5 ...

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ATtiny11/12 72 Figure 52. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE 0.5 Figure 53. I/O Pin Source ...

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Figure 54. I/O Pin Input Threshold Voltage vs. V I/O PIN INPUT THRESHOLD VOLTAGE vs. V 2.5 2 1.5 1 0.5 0 2.7 Figure 55. I/O Pin Input Hysteresis vs. V I/O PIN INPUT HYSTERESIS vs. V 0.18 0.16 ...

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ATtiny12 Typical Characteristics ATtiny11/12 74 The following charts show typical behavior. These data are characterized, but not tested. All current consumption measurements are performed with all I/O pins config- ured as inputs and with internal pull-ups enabled. A sine wave ...

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Figure 57. Active Supply Current vs. V ACTIVE SUPPLY CURRENT vs. V DEVICE CLOCKED BY 32KHz CRYSTAL 140 120 100 1.5 2 2.5 3 Figure 58. Idle Supply Current vs. V IDLE SUPPLY CURRENT ...

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ATtiny11/12 76 Figure 59. Idle Supply Current vs. V IDLE SUPPLY CURRENT vs. V DEVICE CLOCKED BY 32KHz CRYSTAL ˚ 1.5 2 2.5 3 ...

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Figure 61. Analog Comparator Offset Voltage vs. Common Mode Voltage ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE 0.5 1 Common Mode Voltage (V) Figure 62. Analog Comparator Input Leakage Current ANALOG ...

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ATtiny11/12 78 Figure 63. Calibrated RC Oscillator Frequency vs. V CALIBRATED RC OSCILLATOR FREQUENCY vs. OPERATING VOLTAGE 1.22 1.2 1.18 1.16 1.14 1.12 1.1 1.08 1.06 2 2.5 3 3.5 Figure 64. Watchdog Oscillator Frequency vs. V WATCHDOG OSCILLATOR FREQUENCY ...

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Sink and source capabilities of I/O ports are measured on one pin at a time. Figure 65. Pull-up Resistor Current vs. Input Voltage (V 120 ˚ A 100 ˚ ...

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ATtiny11/12 80 Figure 67. I/O Pin Sink Current vs. Output Voltage ( 0.5 1 Figure 68. I/O Pin Source Current vs. Output Voltage ( ˚ A ...

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Figure 69. I/O Pin Sink Current vs. Output Voltage ( 0.5 Figure 70. I/O Pin Source Current vs. Output Voltage ( ˚ ...

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ATtiny11/12 82 Figure 71. I/O Pin Input Threshold Voltage vs. V 2.5 2 1.5 1 0.5 0 2.7 Figure 72. I/O Pin Input Hysteresis vs. V 0.18 0.16 0.14 0.12 0.1 0.08 0.06 0.04 0. 25°C) ...

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Register Summary ATtiny11 Address Name Bit 7 $3F SREG I $3E Reserved $3D Reserved $3C Reserved $3B GIMSK - $3A GIFR - $39 TIMSK - $38 TIFR - $37 Reserved $36 Reserved $35 MCUCR - $34 MCUSR - $33 TCCR0 ...

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Register Summary ATtiny12 Address Name Bit 7 $3F SREG I $3E Reserved $3D Reserved $3C Reserved $3B GIMSK - $3A GIFR - $39 TIMSK - $38 TIFR - $37 Reserved $36 Reserved $35 MCUCR - $34 MCUSR - $33 TCCR0 ...

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Instruction Set Summary Mnemonics Operands Description ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers ADC Rd, Rr Add with Carry two Registers SUB Rd, Rr Subtract two Registers SUBI Rd, K Subtract Constant from Register SBC Rd, Rr ...

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Instruction Set Summary (Continued) Mnemonics Operands Description DATA TRANSFER INSTRUCTIONS LD Rd,Z Load Register Indirect ST Z,Rr Store Register Indirect MOV Rd, Rr Move Between Registers LDI Rd, K Load Immediate IN Rd Port OUT P, Rr Out ...

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Ordering Information ATtiny11 Power Supply Speed (MHz) 2.7 - 5.5V 4.0 - 5.5V Notes: 1. The speed grade refers to maximum clock rate when using an external crystal or external clock drive. The internal RC oscil- lator has the same ...

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... Package ATtiny12V-1PC 8P3 ATtiny12V-1SC 8S2 ATtiny12V-1PI 8P3 (2) ATtiny12V-1PU 8P3 ATtiny12V-1SI 8S2 (2) ATtiny12V-1SU 8S2 ATtiny12L-4PC 8P3 ATtiny12L-4SC 8S2 ATtiny12L-4PI 8P3 (2) ATtiny12L-4PU 8P3 ATtiny12L-4SI 8S2 (2) ATtiny12L-4SU 8S2 ATtiny12-8PC 8P3 ATtiny12-8SC 8S2 ATtiny12-8PI 8P3 (2) ATtiny12-8PU 8P3 ATtiny12-8SI 8S2 (2) ATtiny12-8SU 8S2 Package Type Operation Range Commercial (0° ...

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Packaging Information 8P3 Top View PLCS Side View Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information. 2. Dimensions A and L are measured with the ...

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Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. 2. Mismatch of the upper and lower dies and resin burrs are not included recommended that upper ...

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Datasheet Revision History Rev. 1006F-06/07 Rev. 1006E-07/06 Rev. 1006D-07/03 Rev. 1006C-09/01 1006F–AVR–06/07 Please note that the page numbers listed in this section are refering to this document. The revision numbers are referring to the document revision. 1. “Not recommended for ...

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Table of Contents 1006F–AVR–06/07 Features................................................................................................. 1 Pin Configuration.................................................................................. 1 Description ............................................................................................ 2 ATtiny11 Block Diagram ....................................................................................... 2 ATtiny12 Block Diagram ....................................................................................... 4 Pin Descriptions.................................................................................................... 5 Clock Options ....................................................................................................... 5 Architectural Overview......................................................................... 8 General-purpose Register File.............................................................................. 9 ALU – Arithmetic Logic ...

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ATtiny11/12 ii High-voltage Serial Programming Algorithm....................................................... 49 High-voltage Serial Programming Characteristics .............................................. 52 Low-voltage Serial Downloading (ATtiny12 only) ............................................... 52 Low-voltage Serial Programming Characteristics............................................... 56 Electrical Characteristics................................................................... 57 Absolute Maximum Ratings ................................................................................ 57 DC Characteristics – Preliminary Data ............................................................... 57 ...

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... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...