P89CV51RC2FA NXP Semiconductors, P89CV51RC2FA Datasheet
P89CV51RC2FA
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P89CV51RB2/RC2/RD2 8-bit 80C51 5 V low power 64 kB flash microcontroller with 1 kB RAM, SPI, 6-clock CPU with 6/12-clock peripherals Rev. 03 — 25 August 2009 1. General description The P89CV51RB2/RC2/RD2 are three types of 80C51 microcontroller with respectively ...
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... Ordering information Table 1. Type number P89CV51RB2FA P89CV51RB2FBC P89CV51RC2FA P89CV51RC2FBC P89CV51RD2FA P89CV51RD2FBC 3.1 Ordering options Table 2. Type number P89CV51RB2FA P89CV51RB2FBC P89CV51RC2FA P89CV51RC2FBC P89CV51RD2FA P89CV51RD2FBC P89CV51RB2_RC2_RD2_3 Product data sheet P89CV51RB2/RC2/RD2 Ordering information Package Name Description PLCC44 plastic leaded chip carrier; 44 leads TQFP44 plastic thin quad flat package; 44 leads; body ...
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... NXP Semiconductors 4. Block diagram P89CV51RB2/RC2/RD2 P3[7:0] P2[7:0] P1[7:0] P0[7:0] XTAL1 CRYSTAL OR RESONATOR XTAL2 Fig 1. Block diagram P89CV51RB2_RC2_RD2_3 Product data sheet P89CV51RB2/RC2/RD2 HIGH PERFORMANCE 80C51 CPU 16 kB/32 kB/64 kB CODE FLASH internal bus 1 kB DATA RAM PORT 3 PORT 2 PORT 1 PORT 0 OSCILLATOR Rev. 03 — 25 August 2009 ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 2. P89CV51RB2_RC2_RD2_3 Product data sheet P1[5]/CEX2/MOSI 7 P1[6]/CEX3/MISO 8 9 P1[7]/CEX4/SPICLK 10 RST P3[0]/RXD 11 P89CV51RB2/RC2/RD2 n. P3[1]/TXD P3[2]/INT0 14 P3[3]/INT1 15 16 P3[4]/T0 17 P3[5]/T1 PLCC44 pin configuration Rev. 03 — 25 August 2009 P89CV51RB2/RC2/RD2 ...
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... NXP Semiconductors Fig 3. 5.2 Pin description Table 3. P89CV51RB2/RC2/RD2 Pin description Symbol Pin PLCC44 TQFP44 P0[0] to P0[7] P0[0]/AD0 43 37 P0[1]/AD1 42 36 P0[2]/AD2 41 35 P0[3]/AD3 40 34 P0[4]/AD4 39 33 P0[5]/AD5 38 32 P89CV51RB2_RC2_RD2_3 Product data sheet P1[5]/CEX2/MOSI 1 P1[6]/CEX3/MISO ...
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... NXP Semiconductors Table 3. P89CV51RB2/RC2/RD2 Pin description Symbol Pin PLCC44 TQFP44 P0[6]/AD6 37 31 P0[7]/AD7 36 30 P1[0] to P1[7] P1[0]/ P1[1]/T2EX 3 41 P1[2]/ECI 4 42 P1[3]/CEX0 5 43 P1[4]/CEX1 P1[5]/CEX2 MOSI P1[6]/CEX3 MISO P1[7]/CEX4 SPICLK P2[0] to P2[7] ...
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... NXP Semiconductors Table 3. P89CV51RB2/RC2/RD2 Pin description Symbol Pin PLCC44 TQFP44 P2[1]/ P2[2]/A10 26 20 P2[3]/A11 27 21 P2[4]/A12 28 22 P2[5]/A13 29 23 P2[6]/A14 30 24 P2[7]/A15 31 25 P3[0] to P3[7] P3[0]/RXD 11 5 P3[1]/TXD 13 7 P3[2]/INT0 14 8 P3[3]/INT1 ...
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... NXP Semiconductors Table 3. P89CV51RB2/RC2/RD2 Pin description Symbol Pin PLCC44 TQFP44 RST ALE 33 27 XTAL1 21 15 XTAL2 [1] ALE loading issue: When ALE pin experiences higher loading (> 30 pF) during the reset, the microcontroller may accidentally enter into modes other than normal working mode. The solution is to add a pull-up resistor from between e.g., ALE pin and V ...
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... NXP Semiconductors 6. Functional description 6.1 Special function registers Remark: SFR accesses are restricted in the following ways: • Do not attempt to access any SFR locations that are undefined. • Access to defined SFR locations must be strictly for the functions of the SFRs. • ...
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Table 4. Special function registers * indicates SFRs that are bit addressable. Name Description SFR address Bit address ACC* Accumulator AUXR Auxiliary function Register AUXR1 Auxiliary function Register 1 Bit address B* B register CCAP0H Module 0 Capture High CCAP1H ...
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Table 4. Special function registers …continued * indicates SFRs that are bit addressable. Name Description SFR address DPTR Data Pointer (2 B) DPH Data Pointer High DPL Data Pointer Low Bit address IE* Interrupt Enable Bit address IP* Interrupt Priority ...
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Table 4. Special function registers …continued * indicates SFRs that are bit addressable. Name Description SFR address Bit address SPCR SPI Control Register SPSR SPI Status Register SPDAT SPI Data SP Stack Pointer Bit address TCON* Timer/counter Control Bit address ...
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... NXP Semiconductors 6.2 Memory organization The various P89CV51RB2/RC2/RD2 memory spaces are as follows: • DATA 128 B of internal data memory space (00H:7FH) accessed via direct or indirect addressing, using instructions other than MOVX and MOVC. All or part of the stack may be in this area. ...
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... NXP Semiconductors The DPTR points to location 0A0H and the data in the accumulator is written to address 0A0H of the expanded RAM rather than off-chip external memory. Access to EXTRAM addresses that are not present on the device (above 2FFH) will access external off-chip memory and will perform in the same way as the standard 8051, with P0 and P2 as data/address bus, and P3[6] and P3[7] as write and read timing signals ...
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... NXP Semiconductors 2FFH 000H Fig 4. 6.2.2 Dual data pointers The device has two 16-bit data pointers. The DPTR Select (DPS) bit in AUXR1 determines which of the two data pointers is accessed. When DPS = 0, DPTR0 is selected; when DPS = 1, DPTR1 is selected. Quickly switching between the two data pointers can be accomplished by a single INC instruction on AUXR1 ...
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... NXP Semiconductors Fig 5. Table 8. Not bit addressable; reset value 00H. Bit Symbol Table 9. Bit 6.2.3 Reset At initial power-up, the port pins will random state until the oscillator has started and the internal reset algorithm has weakly pulled all pins HIGH. Powering up the device without a valid reset could cause the MCU to start executing instructions from an indeterminate location. Such undefi ...
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... NXP Semiconductors Following a reset condition, under normal conditions, the MCU will start executing code from address 0000H in the user’s code memory. However if either the PSEN pin was LOW when reset was exited, or the status bit = 1, the MCU will start executing code from the boot address ...
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... NXP Semiconductors • Programming with industry-standard commercial programmers. • 10000 typical erase/program cycles for each byte. • 100 year minimum data retention. 6.3.3 Boot block When the microcontroller programs its own flash memory, all of the low-level details are handled by code (bootloader) that is contained in a boot block. A user program calls the common entry point in the boot block with appropriate parameters to accomplish the desired operation ...
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... NXP Semiconductors 6.3.7 Using ISP The ISP feature allows for a wide range of baud rates to be used in your application, independent of the oscillator frequency also adaptable to a wide range of oscillator frequencies. This is accomplished by measuring the bit-time of a single bit in a received character. This information is then used to program the baud rate in terms of timer counts based on the oscillator frequency ...
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... NXP Semiconductors Table 11. Record type P89CV51RB2_RC2_RD2_3 Product data sheet P89CV51RB2/RC2/RD2 ISP Hex record formats Command/data function Program user code memory :nnaaaa00dd..ddcc Where number of bytes to program aaaa = address dd..dd = data bytes cc = checksum Example: :09000000010203040506070809CA End of File (EOF), no operation :xxxxxx01cc Where: xxxxxx = required field but value is a don’t care ...
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... NXP Semiconductors Table 11. Record type 03 P89CV51RB2_RC2_RD2_3 Product data sheet P89CV51RB2/RC2/RD2 ISP Hex record formats …continued Command/data function Miscellaneous write functions :nnxxxx03ffssddcc Where number of bytes in the record xxxx = required field but value is a don’t care ff = subfunction code ss = selection code dd = data (if needed) ...
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... NXP Semiconductors Table 11. Record type 03 (continued) Subfunction code = 01 (erase blocks) P89CV51RB2_RC2_RD2_3 Product data sheet P89CV51RB2/RC2/RD2 ISP Hex record formats …continued Command/data function block code, as shown below block kB, 00H block kB, 20H block kB, 40H block kB, 80H block kB, C0H Subfunction code = 04 (erase boot vector and status bit don’ ...
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... NXP Semiconductors Table 11. Record type P89CV51RB2_RC2_RD2_3 Product data sheet P89CV51RB2/RC2/RD2 ISP Hex record formats …continued Command/data function Display device data or blank check :05xxxx04sssseeeeffcc Where 05 = number of bytes in the record xxxx = required field but value is a don’t care 04 = function code for display or blank check ssss = starting address, MSB fi ...
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... NXP Semiconductors 6.3.8 IAP method Several IAP calls are available for use by an application program to permit selective erasing, reading and programming of flash pages, security bits, status bit, and device ID. All calls are made through a common interface, PGM_MTP. The programming functions are selected by setting up the microcontroller’s registers before making a call to PGM_MTP at FFF0H ...
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... NXP Semiconductors Table 12. IAP function Erase 8 kB/16 kB code block Program user code Read user code Erase status bit and boot vector Program security bits P89CV51RB2_RC2_RD2_3 Product data sheet P89CV51RB2/RC2/RD2 IAP function calls …continued IAP call parameters Input parameters 01H or 81H (WDT feed) ...
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... NXP Semiconductors Table 12. IAP function Program status bit, boot vector, 6 /12 bit Read security bits, status bit, boot vector Erase page 6.4 Timers/counters 0 and 1 The two 16-bit timer/counter registers: Timer 0 and Timer 1 can be configured to operate either as timers or event counters (see In the ‘ ...
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... NXP Semiconductors The ‘Timer’ or ‘Counter’ function is selected by control bits C/T in the special function register TMOD. These two timers/counters have four operating modes, which are selected by bit-pairs (M1, M0) in TMOD. Modes 0, 1, and 2 are the same for both timers/counters. Mode 3 is different. The four operating modes are described in the following text. ...
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... NXP Semiconductors Table 17. Bit 6.4.1 Mode 0 Putting either timer into Mode 0 makes it look like an 8048 timer, which is an 8-bit counter with a fixed divide-by-32 prescaler. osc/6 Tn pin TnGate INTn pin Fig 7. In this mode, the timer register is configured as a 13-bit register. As the count rolls over from all 1s to all 0s, it sets the timer interrupt fl ...
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... NXP Semiconductors 6.4.2 Mode 1 Mode 1 is the same as Mode 0, except that all 16 bits of the timer register (THn and TLn) are used; see osc/6 Tn pin TRn TnGate INTn pin Fig 8. 6.4.3 Mode 2 Mode 2 configures the timer register as an 8-bit counter (TLn) with automatic reload, as shown in contents of THn, which must be preset by software ...
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... NXP Semiconductors TnGate INT0 pin Fig 10. Timer/counter 0 Mode 3 (two 8-bit counters) 6.5 Timer 2 Timer 16-bit timer/counter which can operate as either an event timer or an event counter, as selected by C/T2 in the special function register T2CON. Timer 2 has four operating modes: Capture, Auto-reload (up or down counting), Clock-out, and Baud rate ...
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... NXP Semiconductors Table 20. Bit Table 21. Not bit addressable; reset value: XX00 0000B. Bit Symbol Table 22. Bit 6.5.1 Capture mode In the Capture mode there are two options which are selected by bit EXEN2 in T2CON. If EXEN2 = 0 Timer 16-bit timer or counter (as selected by C/T2 in T2CON) which upon overfl ...
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... NXP Semiconductors OSC 6 T2 pin transition detector T2EX pin Fig 11. Timer 2 in Capture mode There is no reload value for TL2 and TH2 in this mode. Even when a capture event occurs from T2EX, the counter keeps on counting T2 pin transitions or f loaded contents of RCAP2L and RCAP2H registers are not protected, once Timer 2 interrupt is signalled it has to be serviced before a new capture event on T2EX pin occurs ...
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... NXP Semiconductors In this mode, there are two options selected by bit EXEN2 in T2CON register. If EXEN2 = 0, then Timer 2 counts up to 0FFFFH and sets the TF2 (overflow flag) bit upon overflow. This causes the Timer 2 registers to be reloaded with the 16-bit value in RCAP2L and RCAP2H ...
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... NXP Semiconductors 6.5.3 Programmable clock-out duty cycle clock can be programmed to come out on pin T2 (P1[0], Clock-out mode). This pin, besides being a regular I/O pin, has two additional functions. It can be programmed input the external clock for timer/counter output duty cycle clock ranging from 122 MHz MHz operating frequency. To confi ...
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... NXP Semiconductors The Baud rate generator mode is like the Auto-reload mode, when a roll-over in TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L, which are preset by software. The baud rates in modes 1 and 3 are determined by Timer 2’s overflow rate given below: Modes 1 and 3 baud rates = Timer 2 overfl ...
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... NXP Semiconductors Table 23. Rate 750 kBd 19.2 kBd 9.6 kBd 4.8 kBd 2.4 kBd 600 Bd 220 Bd 600 Bd 220 Bd 6.6 UART The UART operates in all standard modes. Enhancements over the standard 80C51 UART include framing error detection, and automatic address recognition. 6.6.1 Mode 0 Serial data enters and exits through RXD, and TXD outputs the shift clock. Only 8 bits are transmitted or received, LSB fi ...
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... NXP Semiconductors Table 24. Bit addressable; reset value: 00H. Bit Symbol Table 25. Bit Table 26. SM0, SM1 6.6.5 Framing error Framing Error (FE) is reported in the SCON.7 bit if SMOD0 (PCON. SMOD0 = 0, SCON.7 is the SM0 bit for the UART recommended that SM0 is set up before SMOD0 is set to 1 ...
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... NXP Semiconductors 6.6.6 More about UART Mode 1 Reception is initiated by a detected 1-to-0 transition at RXD. For this purpose RXD is sampled at a rate of 16 times whatever baud rate has been established. When a transition is detected, the divide-by-16 counter is immediately reset to align its roll-overs with the boundaries of the incoming bit times ...
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... NXP Semiconductors SM2 has no effect in Mode 0, and in Mode 1 can be used to check the validity of the stop bit, although it is preferable to use the Framing Error flag (FE). When the UART receives data in Mode 1 and SM2 = 1, the receive interrupt will not be activated unless a valid stop bit is received ...
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... NXP Semiconductors The following examples help to show the versatility of this scheme. Example 1, slave 0: SADDR = 1100 0000 SADEN = 1111 1101 --------------------------------------------------- - Given = 1100 00X0 Example 2, slave 1: SADDR = 1100 0000 SADEN = 1111 1110 --------------------------------------------------- - Given = 1100 000X In the above example SADDR is the same and the SADEN data is used to differentiate between the two slaves ...
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... NXP Semiconductors address of all don’t cares. This effectively disables the automatic addressing mode and allows the microcontroller to use standard UART drivers which do not make use of this feature. 6.7 Serial Peripheral Interface (SPI) 6.7.1 SPI features • Master or slave operation • ...
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... NXP Semiconductors MSB master LSB 8-BIT SHIFT REGISTER SPI CLOCK GENERATOR Fig 16. SPI master-slave interconnection Table 27. Reset source(s): any reset; reset value: 0000 0000B. Bit Symbol Table 28. Bit Symbol 7 SPIE 6 SPEN 5 DORD 4 MSTR 3 CPOL 2 CPHA 1 SPR1 0 SPR0 Table 29. SPR1 P89CV51RB2_RC2_RD2_3 Product data sheet ...
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... NXP Semiconductors Table 30. Reset source(s): any reset; reset value: 0000 0000B. Bit Symbol Table 31. Bit SCK (CPOL = 0) SCK (CPOL = 1) Fig 17. SPI transfer format with CPHA = 0 SCK (CPOL = 0) SCK (CPOL = 1) Fig 18. SPI transfer format with CPHA = 1 6.8 Watchdog timer The WDT is intended as a recovery method in situations where the CPU may be subjected to software upset ...
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... NXP Semiconductors way to disable the WDT, except through a reset (either a hardware reset or a WDT overflow reset). When the WDT overflows, it will drive an output reset HIGH pulse at the RST pin. When the WDT is enabled (and thus running) the user needs to reset it by writing 01EH and 0E1H, in sequence, to the WDTRST SFR to avoid WDT overfl ...
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... NXP Semiconductors register is set. The CF bit can only be cleared by software. Bits 0 through 4 of the CCON register are the flags for the modules (bit 0 for module 0, bit 1 for module 1, etc.) and are set by hardware when either a match or a capture occurs. These flags can only be cleared by software ...
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... NXP Semiconductors PCA TIMER/COUNTER MODULE0 MODULE1 MODULE2 MODULE3 MODULE4 CMOD.0 ECF Fig 20. PCA interrupt system Table 32. Not bit addressable; reset value: 00H. Bit Symbol Table 33. Bit Table 34. CPS1 0 P89CV51RB2_RC2_RD2_3 Product data sheet P89CV51RB2/RC2/RD2 CCAPMn.0 ECCFn CMOD - PCA counter mode register (address D9H) bit allocation ...
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... NXP Semiconductors Table 34. CPS1 Table 35. Bit addressable; reset value: 00H. Bit Symbol Table 36. Bit Table 37. Not bit addressable; reset value: 00H. Bit Symbol Table 38. Bit P89CV51RB2_RC2_RD2_3 Product data sheet P89CV51RB2/RC2/RD2 CMOD - PCA counter mode register (address D9H) count pulse select CPS0 ...
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... NXP Semiconductors Table 38. Bit Table 39. PCA module modes (CCAPMn register) ECOMn CAPPn CAPNn 6.9.1 PCA capture mode To use one of the PCA modules in the Capture mode CCAPM bits CAPN and CAPP for that module must be set. The external CEX input for the module (on port 1) is sampled for a transition. When a valid transition occurs, the PCA hardware loads the value of the PCA counter registers (CH and CL) into the module’ ...
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... NXP Semiconductors CF CR CEXn - ECOMn 0 Fig 21. PCA Capture mode If the CCFn bit for the module in the CCON SFR and the ECCFn bit in the CCAPMn SFR are set then an interrupt will be generated. 6.9.2 16-bit software timer mode The PCA modules can be used as software timers and MAT bits in the modules CCAPMn register. The PCA timer will be compared to the module’ ...
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... NXP Semiconductors write to CCAPnH reset write to CCAPnL enable 0 1 Fig 22. PCA Compare mode 6.9.3 High-speed output mode In this mode toggle each time a match occurs between the PCA counter and the module’s capture registers. To activate this mode the TOG, MAT, and ECOM bits in the module’s CCAPMn SFR must be set ...
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... NXP Semiconductors write to reset CCAPnH write to CCAPnL enable 0 1 Fig 23. PCA High-speed output mode 6.9.4 Pulse width modulator mode All of the PCA modules can be used as PWM outputs depends on the source for the PCA timer. enable - ECOMn CAPPn 1 Fig 24. PCA PWM mode All of the modules will have the same output frequency because they all share only one PCA timer. The duty cycle of each module is independently variable using the module’ ...
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... NXP Semiconductors module’s CCAPnL SFR, the output will be LOW; when it is equal to, or greater, the output will be HIGH. When CL overflows from FFH to 00H, CCAPnL is reloaded with the value in CCAPnH. This allows the PWM to be updated without glitches. The PWM and ECOM bits in the module’ ...
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... NXP Semiconductors 6.10 Security bits The security bits protect against software piracy and prevent the contents of the flash from being read by unauthorized parties in Parallel programmer mode and ISP mode. Since the end application might need to erase pages and read from the code memory, the security bits have no effect in IAP mode. However, the security bits’ ...
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... NXP Semiconductors 0 INT0# IT0 1 TF0 0 INT1# IT1 1 TF1 ECF CF CCFn ECCFn RI TI SPIF SPIE TF2 EXF2 Fig 25. Interrupt structure Table 42. Bit addressable; reset value: 00H. Bit Symbol Table 43. Bit P89CV51RB2_RC2_RD2_3 Product data sheet IP/IPH/IPA/IPAH IE and IEA registers IE0 IE1 global individual ...
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... NXP Semiconductors Table 43. Bit Table 44. Bit addressable; reset value: 00H. Bit Symbol Table 45. Bit Table 46. Not bit addressable; reset value: 00H. Bit Symbol Table 47. Bit P89CV51RB2_RC2_RD2_3 Product data sheet P89CV51RB2/RC2/RD2 IE - Interrupt enable register 0 (address A8H) bit description Symbol Description ES Serial port interrupt Enable. ...
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... NXP Semiconductors 6.12 Power-saving modes The device provides two power-saving modes of operation for applications where power consumption is critical. The two modes are Idle and Power-down; see 6.12.1 Idle mode Idle mode is entered by setting the IDL bit in the PCON register. In Idle mode, the program counter is stopped ...
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... NXP Semiconductors 6.13 System clock and clock options 6.13.1 Clock input options and recommended capacitor values for oscillator Shown in amplifier (XTAL1, XTAL2), which can be configured for use as an on-chip oscillator. When driving the device from an external clock source, XTAL2 should be left disconnected and XTAL1 should be driven ...
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... NXP Semiconductors 6.13.1.1 Clock control register (CKCON) By default, the device runs at twelve clock cycles per machine cycle (12-clock mode). The device may be run at 6 clock cycles per machine cycle (6-clock mode) by programming of either a non-volatile bit (FX2 SFR bit (X2); see non-volatile bit is programmed, the device will run in 6-clock mode and the X2 SFR bit has no effect ...
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... NXP Semiconductors 7. Limiting values Table 53. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Parameters are valid over operating temperature range unless otherwise specified; all voltages are with respect to V Symbol Parameter T bias ambient temperature amb(bias) T storage temperature ...
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... NXP Semiconductors Table 54. Static characteristics + 4 5 amb DD Symbol Parameter R pull-down resistance pd C input capacitance iss I operating supply current DD(oper) I Idle mode supply current DD(idle) I Power-down mode supply DD(pd) current [1] This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. ...
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... NXP Semiconductors (mA (1) Maximum active I DD (2) Maximum idle I DD (3) Typical active I DD (4) Typical idle I DD Fig 28 function of frequency DD P89CV51RB2_RC2_RD2_3 Product data sheet P89CV51RB2/RC2/RD2 10 20 Rev. 03 — 25 August 2009 80C51 with 1 kB RAM, SPI 002aaa813 (1) (2) (3) ( internal clock frequency (MHz) © NXP B.V. 2009. All rights reserved. ...
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... NXP Semiconductors 9. Dynamic characteristics Table 55. Dynamic characteristics Over operating conditions: load capacitance for port 0, ALE, and PSEN = 100 pF; load capacitance for all other outputs = amb DD Symbol Parameter f oscillator frequency osc t ALE pulse width LHLL t address valid to ALE LOW time ...
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... NXP Semiconductors 9.1 Explanation of symbols Each timing symbol used in always a ‘t’ (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for. ...
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... NXP Semiconductors ALE PSEN RD t LLAX t AVLL port 0 from RI to DPL port 2 Fig 30. External data memory read cycle t LHLL ALE PSEN WR t AVLL from RI or DPL port 0 port 2 Fig 31. External data memory write cycle P89CV51RB2_RC2_RD2_3 Product data sheet t LLDV t t LLWL ...
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... NXP Semiconductors Table 56. External clock drive Symbol Parameter f oscillator frequency osc T clock cycle time cy(clk) t clock HIGH time CHCX t clock LOW time CLCX t clock rise time CLCH t clock fall time CHCL Fig 32. External clock timing (with an amplitude of at least V Table 57. ...
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... NXP Semiconductors instruction ALE clock t QVXH output data write to SBUF t XHDV input data clear RI Fig 33. Shift register mode timing waveforms Table 58. SPI interface timing Symbol Parameter f SPI operating frequency SPI T SPI cycle time SPICYC t SPI enable lead time SPILEAD t SPI enable lag time ...
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... NXP Semiconductors SS SPICLK (CPOL = 0) (output) SPICLK (CPOL = 1) (output) MISO (input) t MOSI SPIF (output) Fig 34. SPI master timing (CPHA = 0) SS SPICLK (CPOL = 0) (output) SPICLK (CPOL = 1) (output) MISO (input) t SPIF MOSI (output) Fig 35. SPI master timing (CPHA = 1) P89CV51RB2_RC2_RD2_3 Product data sheet P89CV51RB2/RC2/RD2 T SPICYC ...
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... NXP Semiconductors SS t SPIR t SPILEAD SPICLK (CPOL = 0) (input) t SPIF SPICLK (CPOL = 1) (input) t SPIA MISO (output) t SPIDSU MOSI (input) Fig 36. SPI slave timing (CPHA = SPIR t SPILEAD SPICLK (CPOL = 0) (input) t SPIF SPICLK (CPOL = 1) (input) t SPIOH t SPIDV t SPIA MISO not defined (output) MOSI (input) Fig 37 ...
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... NXP Semiconductors Fig 38. Test load example Fig 39. I Fig 40. I P89CV51RB2_RC2_RD2_3 Product data sheet to DUT V RST DD (n.c.) XTAL2 clock XTAL1 signal V All other pins disconnected test condition, Active mode DD RST (n.c.) XTAL2 clock XTAL1 signal All other pins disconnected test condition, Idle mode DD Rev. 03 — ...
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... NXP Semiconductors Fig 41. I P89CV51RB2_RC2_RD2_3 Product data sheet RST (n.c.) XTAL2 XTAL1 V SS All other pins disconnected test condition, Power-down mode DD Rev. 03 — 25 August 2009 P89CV51RB2/RC2/RD2 80C51 with 1 kB RAM, SPI DUT 002aad019 © NXP B.V. 2009. All rights reserved. ...
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... NXP Semiconductors 10. Package outline TQFP44: plastic thin quad flat package; 44 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 1.05 1.2 mm 0.25 0.05 0.95 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC ...
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... NXP Semiconductors PLCC44: plastic leaded chip carrier; 44 leads pin 1 index DIMENSIONS (mm dimensions are derived from the original inch dimensions UNIT max. min. 4.57 0.53 mm 0.51 0.25 3.05 4.19 0.33 0.180 0.021 inches 0.02 0.01 0.12 0.165 0.013 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...
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... NXP Semiconductors 11. Abbreviations Table 59. Acronym ALE CPU DPTR DUT EPROM EMI ID IAP ISP LSB MCU MSB PCA PCH PCL PWM RAM RC SFR SPI SRAM UART WDT P89CV51RB2_RC2_RD2_3 Product data sheet P89CV51RB2/RC2/RD2 Abbreviations Description Address Latch Enable Central Processing Unit Data PoinTeR ...
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... NXP Semiconductors 12. Revision history Table 60. Revision history Document ID Release date P89CV51RB2_RC2_RD2_3 20090825 • Modifications: • • • • • P89CV51RB2_RC2_RD2_2 20090422 • Modifications: P89CV51RB2_RC2_RD2_1 20071005 P89CV51RB2_RC2_RD2_3 Product data sheet Data sheet status Product data sheet Table 4: AUXR1, replaced ‘-’ with ‘ENBOOT’. ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 15. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.1 Principal features . . . . . . . . . . . . . . . . . . . . . . . 1 2.2 Additional features . . . . . . . . . . . . . . . . . . . . . . 1 2.3 Comparison to P89C51RB2/RC2/RD2 devices 2 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 3.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Functional description . . . . . . . . . . . . . . . . . . . 9 6.1 Special function registers . . . . . . . . . . . . . . . . . 9 6 ...