EP7311-CV Cirrus Logic Inc, EP7311-CV Datasheet
EP7311-CV
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EP7311-CV Summary of contents
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... Internal Data Bus TM MaverickKey http://www.cirrus.com OVERVIEW The Maverick™ EP7311 is designed for ultra-low-power applications such as PDAs, smart cellular phones, and industrial hand held information appliances. The core-logic functionality of the device is built around an ARM720T processor with four-way set-associative unified cache and a write buffer. Incorporated into the ARM720T is an ...
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... Package — 208-Pin LQFP — 256-Ball PBGA ® support — 204-Ball TFBGA ■ The fully static EP7311 is optimized for low power dissipation and is fabricated on a 0.25 micron CMOS process ■ Development Kits — EDB7312: Development Kit with color STN LCD on board. ...
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... LQFP Package Specifications ......................................................................................................24 208-Pin LQFP Pin Diagram .......................................................................................................................25 208-Pin LQFP Numeric Pin Listing ............................................................................................................26 204-Ball TFBGA Package Characteristics ...........................................................................................................29 204-Ball TFBGA Package Specifications ..................................................................................................29 204-Ball TFBGA Pinout (Top View) ...........................................................................................................30 DS506F1 High-Performance, Low-Power System on Chip © Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) EP7311 3 ...
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... EP7311 High-Performance, Low-Power System on Chip 204-Ball TFBGA Ball Listing ...................................................................................................................... 31 256-Ball PBGA Package Characteristics ............................................................................................................ 38 256-Ball PBGA Package Specifications .................................................................................................... 38 256-Ball PBGA Pinout (Top View)) ............................................................................................................ 39 256-Ball PBGA Ball Listing ........................................................................................................................ 39 JTAG Boundary Scan Signal Ordering ............................................................................................................... 43 CONVENTIONS ................................................................................................................................. 48 Acronyms and Abbreviations .............................................................................................................................. 48 Units of Measurement ......................................................................................................................................... 48 General Conventions .......................................................................................................................................... 49 Pin Description Conventions ............................................................................................................................... 49 Ordering Information ....................................................................................................................... 50 Environmental, Manufacturing, & ...
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... Table 20. 204-Ball TFBGA Ball Listing .........................................................................................................................31 Table 21. 256-Ball PBGA Ball Listing ...........................................................................................................................39 Table 22. JTAG Boundary Scan Signal Ordering .........................................................................................................43 Table 23. Acronyms and Abbreviations ........................................................................................................................48 Table 24. Unit of Measurement .....................................................................................................................................48 Table 25. Pin Description Conventions .........................................................................................................................49 DS506F1 High-Performance, Low-Power System on Chip © Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) EP7311 5 ...
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... IDs such as those assigned for SDMI (Secure Digital Music Initiative) or any other authentication mechanism. 6 Both a specific 32-bit ID as well as a 128-bit random ID is programmed into the EP7311 through the use of laser probing technology. These IDs can then be used to match secure ARM 32-bit RISC ...
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... RISC processor, and the availability of efficient C-compilers and other software development tools, ensures that a wide range of audio decompression algorithms can easily be ported to and run on the EP7311 Universal Asynchronous Receiver/Transmitters (UARTs) The EP7311 includes two 16550-type UARTs for RS-232 serial communications, both of which have two 16-byte FIFOs for receiving and transmitting data ...
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... EP7311 High-Performance, Low-Power System on Chip CODEC Interface The EP7311 includes an interface to telephony-type CODECs for easy integration into voice-over-IP and other voice communications systems. The multiplexed to the same pins as the MCP and SSI2. Pin Mnemonic I/O PCMCLK O Serial bit clock PCMOUT O Serial data out ...
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... Table K. Interrupt Controller Pin Assignments Note: Real-Time Clock The EP7311 contains a 32-bit Real Time Clock (RTC) that can be written to and read from in the same manner as the timer counters. It also contains a 32-bit output match register which can be programmed to generate an interrupt. • ...
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... Internal Boot ROM The internal 128 byte Boot ROM facilitates download of saved code to the on-board SRAM/FLASH. Packaging The EP7311 is available in a 208-pin LQFP package, 256-ball PBGA package or a 204-ball TFBGA package. © Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) ...
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... SIBDOUT SSIRXDA I SIBDIN SSITXFR I/O SIBSYNC SSIRXFR I p/u BUZ O Table R. MCP/SSI2/CODEC Pin Multiplexing DS506F1 The following table shows the pins that have been multiplexed in the EP7311. Signal nMOE nMWE WRITE A[27:15] SSI2 CODEC A[14:13] SSICLK PCMCLK PD[7:6] SSITXDA PCMOUT RUN SSIRXDA ...
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... EP7311 High-Performance, Low-Power System on Chip System Design As shown in system block diagram, simply adding desired memory and peripherals to the highly integrated EP7311 CRYSTAL CRYSTAL PC CARD PC CARD CONTROLLER SOCKET ×16 SDRAM SDRAM ×16 SDRAM SDRAM ×16 FLASH FLASH ×16 FLASH FLASH EXTERNAL MEMORY- ...
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... 100 10.0 © Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) EP7311 Unit Conditions DDIO DDIO VIL to VIH V IOH = 0 IOH = IOH = IOL = –0 IOL = – IOL = –12 mA VIN = V or GND µA DD VOUT = V or GND µ ...
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... EP7311 High-Performance, Low-Power System on Chip Symbol Parameter CI/O Transceiver capacitance Standby current consumption IDD STANDBY Core, Osc, RTC @2 I/O @ 3.3 V Standby current consumption IDD STANDBY Core, Osc, RTC @2 I/O @ 3.3 V Standby current consumption IDD STANDBY Core, Osc, RTC @2 I Idle current consumption ...
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... Unless specified otherwise, the following conditions are true for all timing measurements. All characteristics are specified 3.1 - 3.5 V and over an operating temperature of -40°C to +85°C. Pin loadings is 50 pF. The timing values are DDIO SS referenced to 1 DS506F1 High-Performance, Low-Power System on Chip Figure 2. Legend for Timing Diagrams © Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) EP7311 15 ...
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... EP7311 High-Performance, Low-Power System on Chip SDRAM Interface Figure 3 through Figure 6 define the timings associated with all phases of the SDRAM. The following table contains the values for the timings of each of the SDRAM modes. Parameter SDCLK rising edge to SDCS assert delay time SDCLK rising edge to SDCS deassert delay time ...
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... The SDCLK signal may be phase shifted relative to the rest of the SDRAM control and data signals due to uneven loading. Designers should take care to ensure that delays between SDRAM control and data signals are approximately equal DS506F1 High-Performance, Low-Power System on Chip t CSd t RAd t CAd t ADx t MWd © Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) EP7311 17 ...
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... EP7311 High-Performance, Low-Power System on Chip SDRAM Burst Read Cycle SDCLK t CSa t SDCS CSd t RAa t SDRAS RAd SDCAS t ADv ADRAS ADDR DATA SDQM [0:3] SDMWE Note: 1. Timings are shown with CAS latency = 2 2. The SDCLK signal may be phase shifted relative to the rest of the SDRAM control and data signals due to uneven loading. ...
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... CSa CSa t t CSd CSd t RAd t CAa t CAd t t ADv ADv ADRAS t DAd MWa Figure 5. SDRAM Burst Write Cycle Timing Measurement © Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) High-Performance, Low-Power System on Chip ADCAS DAd DAd DAd MWd EP7311 D4 19 ...
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... EP7311 High-Performance, Low-Power System on Chip SDRAM Refresh Cycle SDCLK SDCS SDRAS SDCAS SDATA ADDR SDQM [3:0] SDMWE Note: 1. Timings are shown with CAS latency = 2 2. The SDCLK signal may be phase shifted relative to the rest of the SDRAM control and data signals due to uneven loading. ...
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... EXPREADY setup to EXPCLK falling edge time EXPCLK falling edge to EXPREADY hold time DS506F1 High-Performance, Low-Power System on Chip Symbol t CSd t CSh MWd t MWh t MOEd t MOEh t HWd t WDd Dnv WRd t EXs t EXh © Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) EP7311 Min Typ Max Unit ...
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... EP7311 High-Performance, Low-Power System on Chip Static Memory Single Read Cycle EXPCLK t CSd nCS nMWE nMOE t HWd HALF- WORD t WDd WORD D EXPRDY t WRd WRITE Figure 7. Static Memory Single Read Cycle Timing Measurement Note: 1. The cycle time can be extended by integer multiples of the clock period ( MHz MHz ...
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... Zero wait states for sequential writes is not permitted for memory devices which use nMWE pin, as this cannot be driven with valid timing under zero wait state conditions. 3. Address, Data, Halfword, Word, and Write hold state until next cycle. DS506F1 t CSd MWd MWh EXs EXh © Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) High-Performance, Low-Power System on Chip t CSh EP7311 23 ...
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... EP7311 High-Performance, Low-Power System on Chip Static Memory Burst Read Cycle EXPCLK t CSd nCS nMWE t MOEd nMOE t HWd HALF WORD t WORD WDd D EXPRDY t WRd WRITE Note: 1. Four cycles are shown in the above diagram (minimum wait states, 1-0-0-0). This is the maximum number of consecutive cycles that can be driven ...
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... Address, Data, Halfword, Word, and Write hold state until next cycle. DS506F1 MWd t t MWh MWh Dnv Dv Dnv t EXh Figure 10. Static Memory Burst Write Cycle Timing Measurement © Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) High-Performance, Low-Power System on Chip MWd MWd t MWh Dnv Dv EP7311 t CSh t MWh 25 ...
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... EP7311 High-Performance, Low-Power System on Chip SSI1 Interface Parameter ADCCLK falling edge to nADCCSS deassert delay time ADCIN data setup to ADCCLK rising edge time ADCIN data hold from ADCCLK rising edge time ADCCLK falling edge to data valid delay time ADCCLK falling edge to data invalid delay time ...
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... Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) High-Performance, Low-Power System on Chip Symbol Min Max t 185 2050 clk_per t 925 1025 clk_high t 925 1025 clk_low clkrf FRd FRa t 960 990 FR_per RXs RXh TXd t 960 990 TXv t clk_high clk_low EP7311 Unit ...
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... EP7311 High-Performance, Low-Power System on Chip LCD Interface Parameter CL[2] falling to CL[1] rising delay time CL[1] falling to CL[2] rising delay time CL[1] falling to FRM transition time CL[1] falling to M transition time CL[2] rising to DD (display data) transition time CL[2] t CL1d CL[1] FRM ...
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... TCK TMS TDI t JPzx TDO DS506F1 High-Performance, Low-Power System on Chip Symbol t clk_per t clk_high t clk_low t JPs t JPh t JPco t JPzx t JPxz t JPh t JPs t JPco Figure 14. JTAG Timing Measurement © Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) EP7311 Min Max Units JPxz 29 ...
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... Pin 1 Indicator 1.35 (0.053) 0.45 (0.018) 1.45 (0.057) 0.75 (0.030) Figure 15. 208-Pin LQFP Package Outline Drawing Figure 16. For pin descriptions see the EP7311 User’s Manual. © Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) 27.80 (1.094) 28.20 (1.110) 1.00 (0.039) BSC 0° ...
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... Figure 16. 208-Pin LQFP (Low Profile Quad Flat Pack) Pin Diagram Note: 1. N/C should not be grounded but left as no connects. 2. Pin differences between the EP7211 and the EP7311 are bolded. DS506F1 High-Performance, Low-Power System on Chip EP7311 208-Pin LQFP (Top View) © ...
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... EP7311 High-Performance, Low-Power System on Chip 208-Pin LQFP Numeric Pin Listing Table T. 208-Pin LQFP Numeric Pin Listing Pin Signal Type No. 1 nCS[ VDDIO Pad Pwr 3 VSSIO Pad Gnd 4 EXPCLK I/O 5 WORD Out 6 WRITE/nSDRAS Out 7 RUN/CLKEN O 8 EXPRDY I 9 TXD[ RXD[ TDI I 12 ...
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... Pad Pwr VSSIO Pad Gnd D[11] I/O 1 A[10 D[10] I D[9] I D[8] I/O 1 EP7311 Reset State Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low ...
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... EP7311 High-Performance, Low-Power System on Chip Table T. 208-Pin LQFP Numeric Pin Listing (Continued) Pin Signal Type No. 148 A[7] O 149 VSSIO Pad Gnd 150 D[7] I/O 151 nBATCHG I 152 nEXTPWR I 153 BATOK I 154 nPOR I nMEDCHG/ 155 I nBROM 156 nURESET I 157 VDDOSC Osc Pwr ...
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... SEATING PLANE C DS506F1 Ø0. Ø0.25~0.35(204X Figure 17. 204-Ball TFBGA Package © Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) High-Performance, Low-Power System on Chip BOTTOM VIEW A1 CORNER 0.65 12.35 13±0.05 Substrate Thickness : Ball Pitch : 0.65 Ball Diameter : Mold Thickness : 0.3 EP7311 0.36 0.53 35 ...
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... EP7311 High-Performance, Low-Power System on Chip 204-Ball TFBGA Pinout (Top View nMWE/ A VDDIO EXPCLK nCS3 nCS1 SDQM2 nSDCS1 nSDWE nMOE/ B WORD VDDIO nCS5 nCS2 SDCKE nSDCS0 nSDCAS RUN/ C EXPRDY VDDIO nCS4 nCS0 SDCLK SDQM3 CLKEN D PB7 RXD2 VDDIO WRITE/ E PB4 TXD2 nSDRAS ...
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... System byte address Power fail sense input Main oscillator out I/O ground I/O ground I/O ground Word access select output Digital I/O power, 3.3 V Chip select 5 Chip select 2 ROM, expansion OP enable/SDRAM CAS control signal SDRAM clock enable output SDRAM chip select 0 EP7311 37 ...
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... EP7311 High-Performance, Low-Power System on Chip Table 21. 204-Ball TFBGA Ball Listing (Continued) Ball Location Name Strength B8 DD[ B10 CL[2] B11 D[0] B12 A[1] B13 D[3] B14 A[4] B15 D[6] B16 WAKEUP Schmitt B17 MOSCIN B18 VSSIO B19 VSSIO B20 nURESET Schmitt C1 RUN/CLKEN ...
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... Data I/O GPIO port B GPIO port B JTAG data input Data I/O System byte address Data I/O GPIO port B GPIO port B Data I/O System byte address Data I/O GPIO port A JTAG data out GPIO port B System byte address EP7311 39 ...
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... EP7311 High-Performance, Low-Power System on Chip Table 21. 204-Ball TFBGA Ball Listing (Continued) Ball Location Name Strength H19 D[12] H20 A[12] J1 PA[4] J2 PA[5] J3 PA[6] J18 A[11] J19 D[13] J20 A[13]/DRA[14] K1 PA[1] K2 PA[2] K3 VDDIO K18 D[14] K19 A[14]/DRA[13] K20 D[15] L1 TXD[1] L2 LEDDRV ...
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... Data I/O Data I/O System byte address / SDRAM address Real time clock ground Real time clock oscillator output Real time clock oscillator input Halfword access select output Data I/O System byte address / SDRAM address Real time clock power, 2.5V EP7311 41 ...
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... EP7311 High-Performance, Low-Power System on Chip Table 21. 204-Ball TFBGA Ball Listing (Continued) Ball Location Name Strength V2 VSSIO V3 VSSIO V4 PD[7]/SDQM[1] V5 PD[4] V6 PD[2] V7 SSICLK V8 SSIRXDA V9 nADCCS V10 VDDIO V11 ADCCLK V12 COL[7] V13 COL[4] V14 TCLK V15 BUZ V16 D[29] V17 A[26]/DRA[1] ...
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... SSI1 ADC serial input Digital core power, 2.5V PWM drive output SSI1 ADC sample clock PWM feedback input Keyboard scanner column drive Keyboard scanner column drive Keyboard scanner column drive Data I/O Data I/O Data I/O System byte address / SDRAM address EP7311 43 ...
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... PBGA Package Characteristics 256-Ball PBGA Package Specifications Note: 1) For pin locations see Table 2) Dimensions are in millimeters (inches), and controlling dimension is millimeter 3) Before beginning any new EP7311 design, contact Cirrus Logic for the latest package information. 256-Ball PBGA Pinout (Top View ...
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... Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) High-Performance, Low-Power System on Chip 0.85 (0.034) ±0.05 (.002) 0.40 (0.016) ±0.05 (.002) 30° TYP 2 Layer 0.36 (0.014) ±0.09 (0.004) SIDE VIEW Pin 1 Corner 17.00 (0.669) JEDEC #: MO-151 Ball Diameter: 0.50 mm ± 0. ¥ 17 ¥ 1.61 mm body EP7311 45 ...
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... EP7311 High-Performance, Low-Power System on Chip 256-Ball PBGA Ball Listing The list is ordered by ball location. Table V. 256-Ball PBGA Ball Listing Ball Location Name Type A1 VDDIO Pad power Digital I/O power, 3.3V A2 nCS[4] O Chip select out A3 nCS[1] O Chip select out A4 SDCLK O SDRAM clock out ...
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... System byte address / SDRAM address O System byte address / SDRAM address I Test mode select input I External interrupt input VDDIO Pad power Digital I/O power, 3.3V I GPIO port E / Boot mode select TMS I JTAG mode select VDDIO Pad power Digital I/O power, 3.3V EP7311 47 ...
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... EP7311 High-Performance, Low-Power System on Chip Table V. 256-Ball PBGA Ball Listing (Continued) Ball Location Name Type M7 SSITXFR I/O MCP/CODEC/SSI2 frame sync M8 DRIVE[1] I/O PWM drive output M9 FB[0] I PWM feedback input M10 COL[0] O Keyboard scanner column drive M11 D[27] I/O Data I/O M12 ...
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... N2 M1 nTEST0 R3 K6 EINT3 P1 M2 nEINT2 P2 L4 nEINT1 © Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) High-Performance, Low-Power System on Chip Type Position I/O 17 I/O 20 I/O 23 I/O 26 I/O 29 I/O 32 I/O 35 I/O 38 I/O 41 I/O 44 I/O 47 I/O 50 I/O 53 I/O 56 I EP7311 49 ...
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... EP7311 High-Performance, Low-Power System on Chip Table W. JTAG Boundary Scan Signal Ordering (Continued) LQFP TFBGA Pin No 100 101 50 PBGA Signal Ball Ball T3 N1 nEXTFIQ R1 L5 PE[2]/CLKSEL R2 N2 PE[1]/BOOTSEL1 T1 M4 PE[0]/BOOTSEL0 T2 T2 PD[7]/SDQM[ PD[6/SDQM[0 PD[ PD[ PD[ PD[ PD[ PD[0]/LEDFLSH W6 T6 ...
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... O 209 I/O 211 O 214 I/O 216 O 219 I/O 221 O 224 I/O 226 O 229 I/O 231 O 234 I/O 236 O 239 I/O 241 O 244 I/O 246 O 249 I/O 251 O 254 I/O 256 O 259 I/O 261 O 264 I/O 266 O 269 I/O 271 EP7311 51 ...
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... EP7311 High-Performance, Low-Power System on Chip Table W. JTAG Boundary Scan Signal Ordering (Continued) LQFP TFBGA Pin No. 148 150 151 152 153 154 155 156 161 162 163 164 165 166 169 170 171 172 173 175 176 177 178 179 184 185 ...
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... Table W. JTAG Boundary Scan Signal Ordering (Continued) LQFP TFBGA Pin No. 201 202 204 205 206 207 208 1) See EP7311 Users’ Manual for pin naming / functionality. 2) For each pad, the JTAG connection ordering is input, output, then enable as applicable. DS506F1 PBGA Signal Ball Ball A7 D6 nMWE/nSDWE ...
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... EP7311 High-Performance, Low-Power System on Chip CONVENTIONS This section presents acronyms, abbreviations, units of measurement, and conventions used in this data sheet. Acronyms and Abbreviations Table X lists abbreviations and acronyms used in this data sheet. Table X. Acronyms and Abbreviations Acronym/ Definition Abbreviation A/D analog-to-digital ADC ...
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... Registers are referred to by acronym, with bits listed in brackets separated by a colon (:) (for example, CODR[7:0]), and are described in the EP7311 User’s Manual. The use of “TBD” indicates values that are “to be determined,” “n/a” designates “not available,” and “n/c” indicates a pin that is a “ ...
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... EP7311-IB-90 (90 MHz) EP7311-CV EP7311-IV EP7311-CR EP7311-CR-90 (90 MHz) Environmental, Manufacturing, & Handling Information Model Number EP7311-CB EP7311-CB-90 (90 MHz) EP7311-IB EP7311-IB-90 (90 MHz) EP7311-CV EP7311-IV EP7311-CR EP7311-CR-90 (90 MHz) * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. 56 Temperature 0 to +70 °C -40 to +85 ° +70 °C -40 to +85 ° +70 °C ...
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... SPI is a trademark of Motorola, Inc. Microwire is a trademark of National Semiconductor Corporation. LINUX is a registered trademark of Linus Torvalds. Microsoft Windows and Microsoft are registered trademarks of Microsoft Corporation. DS506F1 High-Performance, Low-Power System on Chip Changes © Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) EP7311 57 ...
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... EP7311 High-Performance, Low-Power System on Chip 58 © Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) DS506F1 ...