ISPLSI 1032E-70LTI LATTICE SEMICONDUCTOR, ISPLSI 1032E-70LTI Datasheet

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ISPLSI 1032E-70LTI

Manufacturer Part Number
ISPLSI 1032E-70LTI
Description
CPLD ispLSI® 1000E Family 6K Gates 128 Macro Cells 70MHz EECMOS Technology 5V 100-Pin TQFP
Manufacturer
LATTICE SEMICONDUCTOR
Datasheet

Specifications of ISPLSI 1032E-70LTI

Package
100TQFP
Family Name
ispLSI® 1000E
Device System Gates
6000
Number Of Macro Cells
128
Maximum Propagation Delay Time
17.5 ns
Number Of User I/os
64
Number Of Logic Blocks/elements
32
Typical Operating Supply Voltage
5 V
Maximum Operating Frequency
70 MHz
Operating Temperature
-40 to 85 °C
• HIGH DENSITY PROGRAMMABLE LOGIC
• HIGH PERFORMANCE E
• IN-SYSTEM PROGRAMMABLE
• OFFERS THE EASE OF USE AND FAST SYSTEM
1032e_09
Copyright © 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
Features
— 6000 PLD Gates
— 64 I/O Pins, Eight Dedicated Inputs
— 192 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
— Small Logic Block Size for Random Logic
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
— In-System Programmable (ISP™) 5V Only
— Increased Manufacturing Yields, Reduced Time-to-
— Reprogram Soldered Devices for Faster Prototyping
— Complete Programmable Device Can Combine Glue
— Enhanced Pin Locking Capability
— Four Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
— Lead-Free Package Options
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
Machines, Address Decoders, etc.
f
t
Market and Improved Product Quality
Logic and Structured Designs
Minimize Switching Noise
Interconnectivity
max = 125 MHz Maximum Operating Frequency
pd = 7.5 ns Propagation Delay
2
CMOS
®
TECHNOLOGY
1
In-System Programmable High Density PLD
The ispLSI 1032E is a High Density Programmable Logic
Device containing 192 Registers, 64 Universal I/O pins,
eight Dedicated Input pins, four Dedicated Clock Input
pins and a Global Routing
provides complete interconnectivity between all of these
elements. The ispLSI 1032E device offers 5V non-vola-
tile in-system programmability of the logic, as well as the
interconnects to provide truly reconfigurable systems. A
functional superset of the ispLSI 1032 architecture, the
ispLSI 1032E device adds two new global output enable
pins.
The basic unit of logic on the ispLSI 1032E device is the
Generic Logic Block (GLB). The GLBs are labeled A0,
A1…D7 (see Figure 1). There are a total of 32 GLBs in the
ispLSI 1032E device. Each GLB has 18 inputs, a pro-
grammable AND/OR/Exclusive OR array, and four outputs
which can be configured to be either combinatorial or
registered. Inputs to the GLB come from the GRP and
dedicated inputs. All of the GLB outputs are brought back
into the GRP so that they can be connected to the inputs
of any GLB on the device.
Functional Block Diagram
Description
A1
A2
A3
A4
A5
A6
A7
A0
D7 D6 D5 D4 D3 D2 D1 D0
B0 B1 B2 B3 B4 B5 B6 B7
Global Routing Pool (GRP)
Output Routing Pool
Output Routing Pool
ispLSI
Logic
Array
D Q
D Q
D Q
D Q
Pool (GRP). The GRP
GLB
®
1032E
CLK
C7
C6
C5
C4
C3
C2
C1
C0
August 2006
0139A(A1)-isp

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ISPLSI 1032E-70LTI Summary of contents

Page 1

... The basic unit of logic on the ispLSI 1032E device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1…D7 (see Figure 1). There are a total of 32 GLBs in the ispLSI 1032E device ...

Page 2

... GLBs. Delays through the GRP have been equalized to minimize timing skew. Clocks in the ispLSI 1032E device are selected using the Clock Distribution Network. Four dedicated clock pins (Y0, Y1, Y2 and Y3) are brought into the distribution network, and five clock outputs (CLK 0, CLK 1, CLK 2, IOCLK 0 and IOCLK 1) are provided to route clocks to the GLBs and I/O cells ...

Page 3

... IH o Capacitance (T =25 C, f=1.0 MHz) A SYMBOL PARAMETER C Dedicated Input, I/O, Y1, Y2, Y3, Clock Capacitance 1 (Commercial/Industrial Clock Capacitance 2 Data Retention Specifications PARAMETER Data Retention Erase/Reprogram Cycles Specifications ispLSI 1032E 1 +1.0V CC +1.0V CC PARAMETER Commercial T = 0° 70°C A Industrial T = -40° 85°C A TYPICAL MINIMUM 20 10000 3 MIN ...

Page 4

... Refer to the Power Consumption CC section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum Specifications ispLSI 1032E Figure 2. Test Load GND to 3.0V -125 ≤ Others ≤ ...

Page 5

... Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock. 2. Refer to Timing Model in this data sheet for further details. 3. Standard 16-bit counter using GRP feedback. 4. Reference Switching Test Conditions section. Specifications ispLSI 1032E Over Recommended Operating Conditions 1 DESCRIPTION ...

Page 6

... Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock. 2. Refer to Timing Model in this data sheet for further details. 3. Standard 16-bit counter using GRP feedback. 4. Reference Switching Test Conditions section. Specifications ispLSI 1032E Over Recommended Operating Conditions 1 DESCRIPTION ...

Page 7

... ORP Bypass Delay orpbp 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros. Specifications ispLSI 1032E 1 DESCRIPTION 3 7 -125 -100 UNITS MIN ...

Page 8

... ORP Delay orp t orpbp 48 ORP Bypass Delay 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros. Specifications ispLSI 1032E -80 -70 -90 MIN. MAX. ...

Page 9

... Clk Delay, Clk GLB to I/O Cell Global Clk Line iocp Global Reset t 59 Global Reset to GLB and I/O Registers gr 1. Internal Timing Parameters are not tested and are for reference only. Specifications ispLSI 1032E 1 DESCRIPTION 9 -125 -100 UNITS MIN. MAX. ...

Page 10

... Clock Delay I/O Cell Global Clock Line t 58 Clock Delay, Clock GLB to I/O Cell Global Clock Line iocp Global Reset Global Reset to GLB and I/O Registers 1. Internal Timing Parameters are not tested and are for reference only. Specifications ispLSI 1032E 1 DESCRIPTION 10 -80 -70 -90 MIN. MAX. MIN. ...

Page 11

... Clock (max) + Reg co + Output gy0(max) + gco + = (#54 + #42 + #56) + (#42) + (#47 + #49) 5 (1.4 + 2.3 + 1.8) + (2.3) + (1.0 + 1.3) 1. Calculations are based upon timing specifications for the ispLSI 1032E-125. Specifications ispLSI 1032E GRP GLB Feedback #34 Comb 4 PT Bypass GRP4 Reg 4 PT Bypass GLB Reg Bypass #30 #35 ...

Page 12

... I can be estimated for the ispLSI 1032E using the following equation (mA PTs * 0.59 nets * Max freq * 0.0078) CC Where PTs = Number of Product Terms used in design # of nets = Number of Signals used in device Max freq = Highest Clock Frequency to the device (in MHz) The I estimate is based on typical conditions ( ...

Page 13

... NC pins are not to be connected to any active signals, Vcc or GND. 2. Pins have dual function capability. 3. Pins have dual function capability which is software selectable. Specifications ispLSI 1032E TQFP PIN NUMBERS Input/Output Pins - These are the general purpose I/O pins used by the logic ...

Page 14

... Pin Configurations ispLSI 1032E 84-Pin PLCC Pinout Diagram VCC 21 GND 22 ispEN 23 RESET 24 1 SDI Pins have dual function capability. 3. Pins have dual function capability which is software selectable. Specifications ispLSI 1032E ispLSI 1032E Top View 14 74 ...

Page 15

... Pin Configurations ispLSI 1032E 100-Pin TQFP Pinout Diagram VCC 12 GND 13 ispEN 14 RESET 15 1 SDI/ I Pins have dual function capability. 2. Pins have dual function capability which is software selectable pins are not to be connected to any active signal, VCC or GND. ...

Page 16

... INDUSTRIAL ORDERING NUMBER 15 ispLSI 1032E-70LJI 15 ispLSI 1032E-70LTI 16 X Grade Blank = Commercial I = Industrial Package J = PLCC T = TQFP JN = Lead-Free PLCC TN = Lead-Free TQFP Power L = Low PACKAGE 84-Pin PLCC 100-Pin TQFP 84-Pin PLCC ...

Page 17

... Ordering Information (Cont.) Lead-Free Packaging FAMILY fmax (MHz) tpd (ns) 125 125 100 ispLSI 100 84-PLCC lead-free package is MSL4. Refer to "Handling Moisture Sensitive Packages" document on www.latticesemi.com. FAMILY fmax (MHz) tpd (ns) 70 ispLSI 70 1. 84-PLCC lead-free package is MSL4. Refer to "Handling Moisture Sensitive Packages" document on www.latticesemi.com. ...

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