LC4256V-75TN100E LATTICE SEMICONDUCTOR, LC4256V-75TN100E Datasheet - Page 2

• Manufacturer Part Number: LC4256V-75TN100E
• Description: CPLD ispMACH® 4000V Family 256 Macro Cells 168MHz EECMOS Technology 3.3V 100-Pin TQFP
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of LC4256V-75TN100E

• Package: 100TQFP
• Family Name: ispMACH® 4000V
• Number Of Macro Cells: 256
• Maximum Propagation Delay Time: 7.5 ns
• Number Of User I/os: 64
• Number Of Logic Blocks/elements: 36
• Typical Operating Supply Voltage: 3.3 V
• Maximum Operating Frequency: 168 MHz
• Number Of Product Terms Per Macro: 80
• Memory Type: EEPROM
• Operating Temperature: -40 to 130 °C

Lattice Semiconductor
Table 2. ispMACH 4000Z Family Selection Guide
ispMACH 4000 Introduction
The high performance ispMACH 4000 family from Lattice offers a SuperFAST CPLD solution. The family is a blend
of Lattice’s two most popular architectures: the ispLSI
the ispMACH 4000 architecture focuses on significant innovations to combine the highest performance with low
power in a flexible CPLD family.
The ispMACH 4000 combines high speed and low power with the flexibility needed for ease of design. With its
robust Global Routing Pool and Output Routing Pool, this family delivers excellent First-Time-Fit, timing predictabil-
ity, routing, pin-out retention and density migration.
The ispMACH 4000 family offers densities ranging from 32 to 512 macrocells. There are multiple density-I/O com-
binations in Thin Quad Flat Pack (TQFP), Chip Scale BGA (csBGA) and Fine Pitch Thin BGA (ftBGA) packages
ranging from 44 to 256 pins/balls. Table 1 shows the macrocell, package and I/O options, along with other key
parameters.
The ispMACH 4000 family has enhanced system integration capabilities. It supports 3.3V (4000V), 2.5V (4000B)
and 1.8V (4000C/Z) supply voltages and 3.3V, 2.5V and 1.8V interface voltages. Additionally, inputs can be safely
driven up to 5.5V when an I/O bank is configured for 3.3V operation, making this family 5V tolerant. The ispMACH
4000 also offers enhanced I/O features such as slew rate control, PCI compatibility, bus-keeper latches, pull-up
resistors, pull-down resistors, open drain outputs and hot socketing. The ispMACH 4000 family members are 3.3V/
2.5V/1.8V in-system programmable through the IEEE Standard 1532 interface. IEEE Standard 1149.1 boundary
scan testing capability also allows product testing on automated test equipment. The 1532 interface signals TCK,
TMS, TDI and TDO are referenced to V
Overview
The ispMACH 4000 devices consist of multiple 36-input, 16-macrocell Generic Logic Blocks (GLBs) interconnected
by a Global Routing Pool (GRP). Output Routing Pools (ORPs) connect the GLBs to the I/O Blocks (IOBs), which
contain multiple I/O cells. This architecture is shown in Figure 1.
Macrocells
I/O + Dedicated Inputs
t
t
t
f
Supply Voltage (V)
Max. Standby Icc (µA)
Pins/Package
PD
S
CO
MAX
(ns)
(ns)
(ns)
(MHz)
ispMACH 4032ZC
32+4/32+4
56 csBGA
48 TQFP
267
2.2
3.5
3.0
1.8
32
20
CC
(logic core).
ispMACH 4064ZC
64+10/64+10
32+4/32+12/
132 csBGA
100 TQFP
56 csBGA
48 TQFP
®
2000 and ispMACH 4A. Retaining the best of both families,
250
3.7
2.5
3.2
1.8
64
25
2
ispMACH 4000V/B/C/Z Family Data Sheet
ispMACH 4128ZC
64+10/96+4
132csBGA
100 TQFP
128
220
4.2
2.7
3.5
1.8
35
ispMACH 4256ZC
64+10/96+6/
132 csBGA
100 TQFP
176 TQFP
128+4
256
200
4.5
2.9
3.8
1.8
55