LC4256V-75TN100E LATTICE SEMICONDUCTOR, LC4256V-75TN100E Datasheet - Page 26

• Manufacturer Part Number: LC4256V-75TN100E
• Description: CPLD ispMACH® 4000V Family 256 Macro Cells 168MHz EECMOS Technology 3.3V 100-Pin TQFP
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of LC4256V-75TN100E

• Package: 100TQFP
• Family Name: ispMACH® 4000V
• Number Of Macro Cells: 256
• Maximum Propagation Delay Time: 7.5 ns
• Number Of User I/os: 64
• Number Of Logic Blocks/elements: 36
• Typical Operating Supply Voltage: 3.3 V
• Maximum Operating Frequency: 168 MHz
• Number Of Product Terms Per Macro: 80
• Memory Type: EEPROM
• Operating Temperature: -40 to 130 °C

Lattice Semiconductor
Timing Model
The task of determining the timing through the ispMACH 4000 family, like any CPLD, is relatively simple. The timing
model provided in Figure 11 shows the specific delay paths. Once the implementation of a given function is deter-
mined either conceptually or from the software report file, the delay path of the function can easily be determined
from the timing model. The Lattice design tools report the timing delays based on the same timing model for a par-
ticular design. Note that the internal timing parameters are given for reference only, and are not tested. The exter-
nal timing parameters are tested and guaranteed for every device. For more information on the timing model and
usage, refer to TN1004,
Figure 11. ispMACH 4000 Timing Model
SCLK
OE
Feedback
IN
From
t
Delays
t
GCLK_IN
In/Out
GOE
t
t
t
IOI
IOI
IN
t
IOI
ispMACH 4000 Timing Model Design and Usage
t
t
INREG
INDIO
Control
t
Delays
ROUTE
t
BLA
t
t
PTCLK
t
t
PTSR
t
BCLK
BSR
MCELL
t
EXP
t
GPTOE
t
PTOE
26
ispMACH 4000V/B/C/Z Family Data Sheet
Routing/GLB Delays
DATA
C.E.
S/R
t
t
PDb
MC Reg.
PDi
Q
Note: Italicized items are optional delay adders.
Register/Latch
Guidelines.
Delays
t
ORP
Delays
In/Out
t
t
t
t
t
FBK
BUF
IOO
DIS
EN
Feedback
Out