XC3S1000-4FG676C

Manufacturer Part NumberXC3S1000-4FG676C
DescriptionFPGA Spartan®-3 Family 1M Gates 17280 Cells 630MHz 90nm Technology 1.2V 676-Pin FBGA
ManufacturerXilinx Inc
XC3S1000-4FG676C datasheets

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Specifications of XC3S1000-4FG676C

Package676FBGAFamily NameSpartan®-3
Device Logic Units17280Device System Gates1000000
Maximum Internal Frequency630 MHzTypical Operating Supply Voltage1.2 V
Maximum Number Of User I/os391Ram Bits442368
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Page 107/217

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R
Assert Low both the chip-select pin, CS_B, and the
read/write control pin, RDWR_B, to write the configuration
data byte presented on the D0-D7 pins to the FPGA on a
rising-edge of the configuration clock, CCLK. The order of
CS_B and RDWR_B does not matter, although RDWR_B
must be asserted throughout the configuration process. If
RDWR_B is de-asserted during configuration, the FPGA
aborts the configuration operation.
After configuration, these pins are available as general-pur-
pose user I/O. However, the SelectMAP configuration inter-
face is optionally available for debugging and dynamic
Table 71: Dual-Purpose Configuration Pins for Parallel (SelectMAP) Configuration Modes
Pin
Name
Direction
D0,
Input during
Configuration Data Port (high nibble):
D1,
configuration
Collectively, the D0-D7 pins are the byte-wide configuration data port for the Parallel
D2,
(SelectMAP) configuration modes. Configuration data is synchronized to the rising edge of
D3
CCLK clock signal.
Output during
The D0-D3 pins are the high nibble of the configuration data byte and located in Bank 4 and
readback
powered by VCCO_4.
The BitGen option Persist permits this pin to retain its configuration function in the User mode.
D4,
Input during
Configuration Data Port (low nibble):
D5,
configuration
The D4-D7 pins are the low nibble of the configuration data byte. However, these signals are
D6,
located in Bank 5 and powered by VCCO_5.
D7
The BitGen option Persist permits this pin to retain its configuration function in the User mode.
Output during
readback
CS_B
Input
Chip Select for Parallel Mode Configuration:
Assert this pin Low, together with RDWR_B to write a configuration data byte from the D0-D7
bus to the FPGA on a rising CCLK edge.
During Readback, assert this pin Low, along with RDWR_B High, to read a configuration data
byte from the FPGA to the D0-D7 bus on a rising CCLK edge.
This signal is located in Bank 5 and powered by VCCO_5.
The BitGen option Persist permits this pin to retain its configuration function in the User mode.
CS_B
DS099-4 (v2.5) December 4, 2009
Product Specification
reconfiguration. To use these SelectMAP pins after configu-
ration, set the Persist bitstream generation option.
The Readback debugging option, for example, requires the
Persist bitstream generation option. During Readback
mode, assert CS_B Low, along with RDWR_B High, to read
a configuration data byte from the FPGA to the D0-D7 bus
on a rising CCLK edge. During Readback mode, D0-D7 are
output pins.
In all the cases, the configuration data and control signals
are synchronized to the rising edge of the CCLK clock sig-
nal.
Description
0
FPGA selected. SelectMAP inputs are valid on the next rising edge of CCLK.
1
FPGA deselected. All SelectMAP inputs are ignored.
www.xilinx.com
Spartan-3 FPGA Family: Pinout Descriptions
Function
107

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