XC3S1000-4FG676C

Manufacturer Part NumberXC3S1000-4FG676C
DescriptionFPGA Spartan®-3 Family 1M Gates 17280 Cells 630MHz 90nm Technology 1.2V 676-Pin FBGA
ManufacturerXilinx Inc
XC3S1000-4FG676C datasheets

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Specifications of XC3S1000-4FG676C

Package676FBGAFamily NameSpartan®-3
Device Logic Units17280Device System Gates1000000
Maximum Internal Frequency630 MHzTypical Operating Supply Voltage1.2 V
Maximum Number Of User I/os391Ram Bits442368
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R
Bitstream Options
Table 79
lists the various bitstream options that affect pins
on a Spartan-3 FPGA. The table shows the names of the
affected pins, describes the function of the bitstream option,
Table 79: Bitstream Options Affecting Spartan-3 Pins
Affected Pin
Name(s)
All unused I/O pins of
For all I/O pins that are unused in the application after
type I/O, DUAL,
configuration, this option defines whether the I/Os are individually
GCLK, DCI, VREF
tied to VCCO via a pull-up resistor, tied ground via a pull-down
resistor, or left floating. If left floating, the unused pins should be
connected to a defined logic level, either from a source internal to
the FPGA or external.
IO_Lxxy_#/DIN,
Serial configuration mode: If set to Yes, then these pins retain their
IO_Lxxy_#/DOUT,
functionality after configuration completes, allowing for device
IO_Lxxy_#/INIT_B
(re-)configuration. Readback is not supported in with serial mode.
IO_Lxxy_#/D0,
Parallel configuration mode (also called SelectMAP): If set to Yes,
IO_Lxxy_#/D1,
then these pins retain their SelectMAP functionality after
IO_Lxxy_#/D2,
configuration completes, allowing for device readback and for
IO_Lxxy_#/D3,
partial or complete (re-)configuration.
IO_Lxxy_#/D4,
IO_Lxxy_#/D5,
IO_Lxxy_#/D6,
IO_Lxxy_#/D7,
IO_Lxxy_#/CS_B,
IO_Lxxy_#/RDWR_B,
IO_Lxxy_#/BUSY,
IO_Lxxy_#/INIT_B
CCLK
After configuration, this bitstream option either pulls CCLK to
VCCAUX via a pull-up resistor, or allows CCLK to float.
CCLK
For Master configuration modes, this option sets the approximate
frequency, in MHz, for the internal silicon oscillator.
PROG_B
A pull-up resistor to VCCAUX exists on PROG_B during
configuration. After configuration, this bitstream option either
pulls PROG_B to VCCAUX via a pull-up resistor, or allows
PROG_B to float.
DONE
After configuration, this bitstream option either pulls DONE to
VCCAUX via a pull-up resistor, or allows DONE to float. See also
DriveDone option.
DONE
If set to Yes, this option allows the FPGA’s DONE pin to drive High
when configuration completes. By default, the DONE is an
open-drain output and can only drive Low. Only single FPGAs and
the last FPGA in a multi-FPGA daisy-chain should use this option.
M2
After configuration, this bitstream option either pulls M2 to
VCCAUX via a pull-up resistor, to ground via a pull-down resistor,
or allows M2 to float.
M1
After configuration, this bitstream option either pulls M1 to
VCCAUX via a pull-up resistor, to ground via a pull-down resistor,
or allows M1 to float.
DS099-4 (v2.5) December 4, 2009
Product Specification
Spartan-3 FPGA Family: Pinout Descriptions
the name of the bitstream generator option variable, and the
legal values for each variable. The default option setting for
each variable is indicated with bold, underlined text.
Bitstream Generation Function
www.xilinx.com
Option
Values
Variable
(default
Name
value)
•
Pulldown
UnusedPin
•
Pullup
•
Pullnone
•
No
Persist
•
Yes
•
No
Persist
•
Yes
•
Pullup
CclkPin
•
Pullnone
ConfigRate
3, 6, 12, 25,
50
•
Pullup
ProgPin
•
Pullnone
•
Pullup
DonePin
•
Pullnone
•
No
DriveDone
•
Yes
•
Pullup
M2Pin
•
Pulldown
•
Pullnone
•
Pullup
M1Pin
•
Pulldown
•
Pullnone
117

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