XC3S1000-4FG676C | |
|---|---|
| Manufacturer Part Number | XC3S1000-4FG676C |
| Description | FPGA Spartan®-3 Family 1M Gates 17280 Cells 630MHz 90nm Technology 1.2V 676-Pin FBGA |
| Manufacturer | Xilinx Inc |
| XC3S1000-4FG676C datasheets |
|
Availability: In stock
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Specifications of XC3S1000-4FG676C | |||
|---|---|---|---|
| Package | 676FBGA | Family Name | Spartan®-3 |
| Device Logic Units | 17280 | Device System Gates | 1000000 |
| Maximum Internal Frequency | 630 MHz | Typical Operating Supply Voltage | 1.2 V |
| Maximum Number Of User I/os | 391 | Ram Bits | 442368 |
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PrevNext
R
FG320: 320-lead Fine-pitch Ball Grid
Array
The 320-lead fine-pitch ball grid array package, FG320,
supports three different Spartan-3 devices, including the
XC3S400, the XC3S1000, and the XC3S1500. The footprint
for all three devices is identical, as shown in
Figure
47.
The FG320 package is an 18 x 18 array of solder balls
minus the four center balls.
All the package pins appear in
Table 97
bank number, then by pin name. Pairs of pins that form a dif-
ferential I/O pair appear together in the table. The table also
shows the pin number for each pin and the pin type, as
defined earlier.
An electronic version of this package pinout table and foot-
print diagram is available for download from the Xilinx web-
site at
http://www.xilinx.com/support/documentation/data_
.
sheets/s3_pin.zip
Pinout Table
Table 97: FG320 Package Pinout
XC3S400
XC3S1000
XC3S1500
Bank
Pin Name
0
IO
0
IO
0
IO/VREF_0
0
IO/VREF_0
0
IO_L01N_0/VRP_0
0
IO_L01P_0/VRN_0
0
IO_L09N_0
0
IO_L09P_0
0
IO_L10N_0
0
IO_L10P_0
0
IO_L15N_0
0
IO_L15P_0
0
IO_L25N_0
0
IO_L25P_0
0
IO_L27N_0
0
IO_L27P_0
0
IO_L28N_0
0
IO_L28P_0
0
IO_L29N_0
0
IO_L29P_0
0
IO_L30N_0
0
IO_L30P_0
0
IO_L31N_0
0
IO_L31P_0/VREF_0
DS099-4 (v2.5) December 4, 2009
Product Specification
Table 97: FG320 Package Pinout (Continued)
Bank
0
Table 97
and
0
0
0
and are sorted by
0
0
1
1
1
1
1
1
1
1
1
1
FG320
1
Pin
1
Number
Type
1
D9
I/O
1
E7
I/O
1
B3
VREF
1
D6
VREF
1
A2
DCI
1
A3
DCI
1
B4
I/O
1
C4
I/O
1
C5
I/O
1
D5
I/O
1
A4
I/O
1
A5
I/O
1
B5
I/O
1
B6
I/O
1
C7
I/O
1
D7
I/O
1
C8
I/O
1
D8
I/O
2
E8
I/O
2
F8
I/O
2
A7
I/O
2
A8
I/O
2
B9
I/O
2
A9
VREF
2
www.xilinx.com
Spartan-3 FPGA Family: Pinout Descriptions
XC3S400
XC3S1000
FG320
XC3S1500
Pin
Pin Name
Number
IO_L32N_0/GCLK7
E9
IO_L32P_0/GCLK6
F9
VCCO_0
B8
VCCO_0
C6
VCCO_0
G8
VCCO_0
G9
IO
A11
IO
B13
IO
D10
IO/VREF_1
A12
IO_L01N_1/VRP_1
A16
IO_L01P_1/VRN_1
A17
IO_L10N_1/VREF_1
A15
IO_L10P_1
B15
IO_L15N_1
C14
IO_L15P_1
C15
IO_L16N_1
A14
IO_L16P_1
B14
IO_L24N_1
D14
IO_L24P_1
D13
IO_L27N_1
E13
IO_L27P_1
E12
IO_L28N_1
C12
IO_L28P_1
D12
IO_L29N_1
F11
IO_L29P_1
E11
IO_L30N_1
C11
IO_L30P_1
D11
IO_L31N_1/VREF_1
A10
IO_L31P_1
B10
IO_L32N_1/GCLK5
E10
IO_L32P_1/GCLK4
F10
VCCO_1
B11
VCCO_1
C13
VCCO_1
G10
VCCO_1
G11
IO
J13
IO_L01N_2/VRP_2
C16
IO_L01P_2/VRN_2
C17
IO_L16N_2
B18
IO_L16P_2
C18
IO_L17N_2
D17
IO_L17P_2/VREF_2
D18
Type
GCLK
GCLK
VCCO
VCCO
VCCO
VCCO
I/O
I/O
I/O
VREF
DCI
DCI
VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VREF
I/O
GCLK
GCLK
VCCO
VCCO
VCCO
VCCO
I/O
DCI
DCI
I/O
I/O
I/O
VREF
147
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