XC3S1000-4FG676C | |
|---|---|
| Manufacturer Part Number | XC3S1000-4FG676C |
| Description | FPGA Spartan®-3 Family 1M Gates 17280 Cells 630MHz 90nm Technology 1.2V 676-Pin FBGA |
| Manufacturer | Xilinx Inc |
| XC3S1000-4FG676C datasheets |
|
Availability: In stock
International delivery:
Warranty: 60 days
×
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Specifications of XC3S1000-4FG676C | |||
|---|---|---|---|
| Package | 676FBGA | Family Name | Spartan®-3 |
| Device Logic Units | 17280 | Device System Gates | 1000000 |
| Maximum Internal Frequency | 630 MHz | Typical Operating Supply Voltage | 1.2 V |
| Maximum Number Of User I/os | 391 | Ram Bits | 442368 |
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PrevNext
R
User I/Os by Bank
Table 100
indicates how the available user-I/O pins are dis-
tributed between the eight I/O banks for the XC3S400 in the
FG456 package. Similarly,
Table 101
Table 100: User I/Os Per Bank for XC3S400 in FG456 Package
I/O
Maximum
Edge
Bank
0
Top
1
2
Right
3
4
Bottom
5
6
Left
7
Table 101: User I/Os Per Bank for XC3S1000, XC3S1500, and XC3S2000 in FG456 Package
Maximum
Edge
I/O Bank
0
Top
1
2
Right
3
4
Bottom
5
6
Left
7
DS099-4 (v2.5) December 4, 2009
Product Specification
able user-I/O pins are distributed between the eight I/O
banks for the XC3S1000, XC3S1500, and XC3S2000 in the
FG456 package.
shows how the avail-
All Possible I/O Pins by Type
I/O
I/O
DUAL
35
27
0
35
27
0
31
25
0
31
25
0
35
21
6
35
21
6
31
25
0
31
25
0
All Possible I/O Pins by Type
I/O
I/O
DUAL
40
31
0
40
31
0
43
37
0
43
37
0
41
26
6
40
25
6
43
37
0
43
37
0
www.xilinx.com
Spartan-3 FPGA Family: Pinout Descriptions
DCI
VREF
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
DCI
VREF
2
5
2
5
2
4
2
4
2
5
2
5
2
4
2
4
GCLK
2
2
0
0
2
2
0
0
GCLK
2
2
0
0
2
2
0
0
159
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|
|
XC3S1000-4FG676I |
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|
 XC3S1000-4FGG456C |
FPGA Spartan®-3 Family 1M Gates 17280 Cells 630MHz 90nm Technology 1.2V 456-Pin FBGA | Xilinx Inc |
|
|
XC3S1000-4FT256C |
FPGA Spartan®-3 Family 1M Gates 17280 Cells 630MHz 90nm Technology 1.2V 256-Pin FTBGA | Xilinx Inc |
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XC3S1000-4FTG256C |
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|
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|
