XC3S1000-4FG676C

Manufacturer Part NumberXC3S1000-4FG676C
DescriptionFPGA Spartan®-3 Family 1M Gates 17280 Cells 630MHz 90nm Technology 1.2V 676-Pin FBGA
ManufacturerXilinx Inc
XC3S1000-4FG676C datasheets

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Specifications of XC3S1000-4FG676C

Package676FBGAFamily NameSpartan®-3
Device Logic Units17280Device System Gates1000000
Maximum Internal Frequency630 MHzTypical Operating Supply Voltage1.2 V
Maximum Number Of User I/os391Ram Bits442368
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Page 33/217

Download datasheet (6Mb)Embed
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R
The DLL component has two clock inputs, CLKIN and
CLKFB, as well as seven clock outputs, CLK0, CLK90,
CLK180, CLK270, CLK2X, CLK2X180, and CLKDV as
described in
Table
15. The clock outputs drive simulta-
neously; however, the High Frequency mode only supports
Table 15: DLL Signals
Signal
Direction
CLKIN
Input
Accepts original clock signal.
CLKFB
Input
Accepts either CLK0 or CLK2X as feed back signal. (Set
CLK_FEEDBACK attribute accordingly).
CLK0
Output
Generates clock signal with same frequency and phase as CLKIN.
CLK90
Output
Generates clock signal with same frequency as CLKIN, only
phase-shifted 90°.
CLK180
Output
Generates clock signal with same frequency as CLKIN, only
phase-shifted 180°.
CLK270
Output
Generates clock signal with same frequency as CLKIN, only
phase-shifted 270°.
CLK2X
Output
Generates clock signal with same phase as CLKIN, only twice the
frequency.
CLK2X180
Output
Generates clock signal with twice the frequency of CLKIN,
phase-shifted 180° with respect to CLKIN.
CLKDV
Output
Divides the CLKIN frequency by CLKDV_DIVIDE value to generate
lower frequency clock signal that is phase-aligned to CLKIN.
The clock signal supplied to the CLKIN input serves as a
reference waveform, with which the DLL seeks to align the
feedback signal at the CLKFB input. When eliminating clock
skew, the common approach to using the DLL is as follows:
The CLK0 signal is passed through the clock distribution
network to all the registers it synchronizes. These registers
are either internal or external to the FPGA. After passing
through the clock distribution network, the clock signal
returns to the DLL via a feedback line called CLKFB. The
control block inside the DLL measures the phase error
between CLKFB and CLKIN. This phase error is a measure
of the clock skew that the clock distribution network intro-
DS099-2 (v2.5) December 4, 2009
Product Specification
Spartan-3 FPGA Family: Functional Description
a subset of the outputs available in the Low Frequency
mode. See
DLL Frequency Modes, page
initialize and report the state of the DLL are discussed in
The Status Logic Component, page
Description
duces. The control block activates the appropriate number
of delay elements to cancel out the clock skew. Once the
DLL has brought the CLK0 signal in phase with the CLKIN
signal, it asserts the LOCKED output, indicating a “lock” on
to the CLKIN signal.
DLL Attributes and Related Functions
A number of different functional options can be set for the
DLL component through the use of the attributes described
in
Table
16. Each attribute is described in detail in the sec-
tions that follow:
www.xilinx.com
35. Signals that
40.
Mode Support
Low
High
Frequency
Frequency
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
Yes
No
Yes
No
Yes
No
Yes
Yes
33

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