XC3S1000-4FG676C

Manufacturer Part NumberXC3S1000-4FG676C
DescriptionFPGA Spartan®-3 Family 1M Gates 17280 Cells 630MHz 90nm Technology 1.2V 676-Pin FBGA
ManufacturerXilinx Inc
XC3S1000-4FG676C datasheets

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Specifications of XC3S1000-4FG676C

Package676FBGAFamily NameSpartan®-3
Device Logic Units17280Device System Gates1000000
Maximum Internal Frequency630 MHzTypical Operating Supply Voltage1.2 V
Maximum Number Of User I/os391Ram Bits442368
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R
Configuration
Spartan-3 FPGAs are programmed by loading configuration
data into robust, reprogrammable, static CMOS configura-
tion latches (CCLs) that collectively control all functional
elements and routing resources. Before powering on the
FPGA, configuration data is stored externally in a PROM or
some other nonvolatile medium either on or off the board.
After applying power, the configuration data is written to the
FPGA using any of five different modes: Master Parallel,
Slave Parallel, Master Serial, Slave Serial, and Boundary
Scan (JTAG). The Master and Slave Parallel modes use an
8-bit-wide SelectMAP port.
Table 2: Signal Standards Supported by the Spartan-3 Family
Standard
Category
Description
Single-Ended
GTL
Gunning Transceiver Logic
HSTL
High-Speed Transceiver Logic
LVCMOS
Low-Voltage CMOS
LVTTL
Low-Voltage Transistor-Transistor Logic
PCI
Peripheral Component Interconnect
SSTL
Stub Series Terminated Logic
Differential
LDT
Lightning Data Transport (HyperTransport™)
(ULVDS)
Logic
LVDS
Low-Voltage Differential Signaling
LVPECL
Low-Voltage Positive Emitter-Coupled Logic
RSDS
Reduced-Swing Differential Signaling
HSTL
Differential High-Speed Transceiver Logic
SSTL
Differential Stub Series Terminated Logic
Notes:
1.
66 MHz PCI is not supported by the Xilinx IP core although PCI66_3 is an available I/O standard.
DS099-1 (v2.5) December 4, 2009
Product Specification
Spartan-3 FPGA Family: Introduction and Ordering Information
The recommended memory for storing the configuration
data is the low-cost Xilinx Platform Flash PROM family,
which includes the XCF00S PROMs for serial configuration
and the higher density XCF00P PROMs for parallel or serial
configuration.
I/O Capabilities
The SelectIO feature of Spartan-3 devices supports 18 sin-
gle-ended standards and 8 differential standards as listed in
Table
2. Many standards support the DCI feature, which
uses integrated terminations to eliminate unwanted signal
reflections.
V
CCO
(V)
Class
N/A
Terminated
Plus
1.5
I
III
1.8
I
II
III
1.2
N/A
1.5
N/A
1.8
N/A
2.5
N/A
3.3
N/A
3.3
N/A
(1)
3.0
33 MHz
1.8
N/A (±6.7 mA)
N/A (±13.4 mA)
2.5
I
II
2.5
N/A
Standard
Bus
Extended Mode
2.5
N/A
2.5
N/A
1.8
II
2.5
II
www.xilinx.com
Symbol
DCI
(IOSTANDARD)
Option
GTL
Yes
GTLP
Yes
HSTL_I
Yes
HSTL_III
Yes
HSTL_I_18
Yes
HSTL_II_18
Yes
HSTL_III_18
Yes
LVCMOS12
No
LVCMOS15
Yes
LVCMOS18
Yes
LVCMOS25
Yes
LVCMOS33
Yes
LVTTL
No
PCI33_3
No
SSTL18_I
Yes
SSTL18_II
No
SSTL2_I
Yes
SSTL2_II
Yes
LDT_25
No
LVDS_25
Yes
BLVDS_25
No
LVDSEXT_25
Yes
LVPECL_25
No
RSDS_25
No
DIFF_HSTL_II_18
Yes
DIFF_SSTL2_II
Yes
5

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