XC3S1000-4FG676C

Manufacturer Part NumberXC3S1000-4FG676C
DescriptionFPGA Spartan®-3 Family 1M Gates 17280 Cells 630MHz 90nm Technology 1.2V 676-Pin FBGA
ManufacturerXilinx Inc
XC3S1000-4FG676C datasheets

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Specifications of XC3S1000-4FG676C

Package676FBGAFamily NameSpartan®-3
Device Logic Units17280Device System Gates1000000
Maximum Internal Frequency630 MHzTypical Operating Supply Voltage1.2 V
Maximum Number Of User I/os391Ram Bits442368
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PrevNext
R
Internal
Logic
V
OUTN
V
OUTP
GND level
Table 37: DC Characteristics of User I/Os Using Differential Signal Standards
(1)
Mask
Signal Standard
Revision
LDT_25 (ULVDS_25)
All
LVDS_25
All
‘E’
(6)
BLVDS_25
All
LVDSEXT_25
All
‘E’
(6)
LVPECL_25
All
(5)
RSDS_25
All
‘E’
DIFF_HSTL_II_18
All
DIFF_SSTL2_II
All
Notes:
1.
Mask revision E devices have tighter output ranges but can be used in any design that was in a previous revision. See
Revisions, page
55.
2.
The numbers in this table are based on the conditions set forth in
3.
This value must be compatible with the receiver to which the FPGA’s output pair is connected.
4.
Output voltage measurements for all differential standards are made with a termination resistor (R
of the differential signal pair.
5.
Only one of the differential standards RSDS_25, LDT_25, LVDS_25, and LVDSEXT_25 may be used for outputs within a bank.
Each differential standard input-pair requires an external 100Ω termination resistor.
6.
Each LVPECL_25 or BLVDS_25 output-pair requires three external resistors for proper output operation as shown in
LVPECL_25 or BLVDS_25 input-pair uses a 100Ω termination resistor at the receiver.
LVPECL
70Ω
Z
0
240Ω
Z
0
70Ω
Figure 32: External Termination Required for LVPECL and BLVDS Output and Input
DS099-3 (v2.5) December 4, 2009
Product Specification
98
Spartan-3 FPGA Family: DC and Switching Characteristics
V
OUTP
V
OUTN
V
50%
OD
V
OCM
V
= Output common mode voltage =
OCM
V
V
= Output differential voltage =
OD
V
= Output voltage indicating a High logic level
OH
= Output voltage indicating a Low logic level
V
OL
Figure 31: Differential Output Voltages
V
OD
Min (mV) Typ (mV)
Max (mV)
Min (V)
(3)
430
600
670
0.495
100
-
600
200
-
500
250
350
450
100
-
600
300
-
700
-
-
-
100
-
600
200
-
500
-
-
-
-
-
-
Table 31
BLVDS
LVPECL
=50Ω
100Ω
=50Ω
www.xilinx.com
P
Differential
I/O Pair Pins
N
V
OH
V
OL
V
+ V
OUTP
OUTN
2
- V
OUTP
OUTN
DS099-3_02_012304
V
V
OCM
OH
Typ (V)
Max (V)
Min (V)
0.600
0.715
0.71
0.80
-
1.6
0.85
1.0
-
1.5
1.10
-
1.20
-
-
0.80
-
1.6
0.85
1.0
-
1.5
1.15
-
-
-
1.35
0.80
-
1.6
0.85
1.0
-
1.5
1.10
-
-
-
V
– 0.40
CCO
-
-
-
V
+ 0.80
TT
and
Table
36.
) of 100Ω across the N and P pins
T
BLVDS
165Ω
Z
=50Ω
0
140Ω
100Ω
Z
=50Ω
0
165Ω
ds099-3_08_112105
V
OL
Max (V)
0.50
1.55
1.40
-
1.55
1.35
1.005
1.55
1.40
0.40
V
– 0.80
TT
Mask and Fab
Figure
32. Each
65

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