XC3S1000-4FG676C | |
|---|---|
| Manufacturer Part Number | XC3S1000-4FG676C |
| Description | FPGA Spartan®-3 Family 1M Gates 17280 Cells 630MHz 90nm Technology 1.2V 676-Pin FBGA |
| Manufacturer | Xilinx Inc |
| XC3S1000-4FG676C datasheets |
|
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Specifications of XC3S1000-4FG676C | |||
|---|---|---|---|
| Package | 676FBGA | Family Name | Spartan®-3 |
| Device Logic Units | 17280 | Device System Gates | 1000000 |
| Maximum Internal Frequency | 630 MHz | Typical Operating Supply Voltage | 1.2 V |
| Maximum Number Of User I/os | 391 | Ram Bits | 442368 |
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PrevNext
Spartan-3 FPGA Family: DC and Switching Characteristics
Timing Measurement Methodology
When measuring timing parameters at the programmable
I/Os, different signal standards call for different test condi-
tions.
Table 47
presents the conditions to use for each stan-
dard.
The method for measuring Input timing is as follows: A sig-
nal that swings between a Low logic level of V
logic level of V
is applied to the Input under test. Some
H
standards also require the application of a bias voltage to
the V
pins of a given bank to properly set the
REF
input-switching threshold. The measurement point of the
Input signal (V
) is commonly located halfway between V
M
and V
.
H
The Output test setup is shown in
Figure
voltage V
is applied to the termination resistor R
T
end of which is connected to the Output. For each standard,
R
and V
generally take on the standard values recom-
T
T
mended for minimizing signal reflections. If the standard
does not ordinarily use terminations (e.g., LVCMOS,
Table 47: Test Methods for Timing Measurement at I/Os
Signal Standard
(IOSTANDARD)
V
REF
Single-Ended
GTL
0.8
GTL_DCI
GTLP
1.0
GTLP_DCI
HSLVDCI_15
0.9
HSLVDCI_18
HSLVDCI_25
HSLVDCI_33
HSTL_I
0.75
HSTL_I_DCI
HSTL_III
0.90
HSTL_III_DCI
HSTL_I_18
0.90
HSTL_I_DCI_18
HSTL_II_18
0.90
HSTL_II_DCI_18
HSTL_III_18
1.1
HSTL_III_DCI_18
LVCMOS12
-
LVCMOS15
-
LVDCI_15
LVDCI_DV2_15
HSLVDCI_15
76
LVTTL), then R
tion, and V
(V
) that was used at the Input is also used at the Output.
M
and a High
L
L
33. A termination
, the other
T
Inputs
(V)
V
(V)
V
(V)
L
H
V
- 0.2
V
+ 0.2
REF
REF
V
- 0.2
V
+ 0.2
REF
REF
V
- 0.5
V
+ 0.5
REF
REF
V
- 0.5
V
+ 0.5
REF
REF
V
- 0.5
V
+ 0.5
REF
REF
V
- 0.5
V
+ 0.5
REF
REF
V
- 0.5
V
+ 0.5
REF
REF
V
- 0.5
V
+ 0.5
REF
REF
0
1.2
0
1.5
www.xilinx.com
is set to 1MΩ to indicate an open connec-
T
is set to zero. The same measurement point
T
V
(V
)
T
REF
FPGA Output
R
(R
)
T
REF
V
(V
)
M
MEAS
C
(C
)
L
REF
ds099-3_07_012004
Notes:
1.
The names shown in parentheses are
used in the IBIS file.
Figure 33: Output Test Setup
Outputs
R
(Ω)
V
(V)
T
T
25
1.2
50
1.2
25
1.5
50
1.5
1M
0
50
0.75
50
1.5
50
0.9
50
0.9
50
1.8
1M
0
1M
0
DS099-3 (v2.5) December 4, 2009
Product Specification
R
Inputs and
Outputs
V
(V)
M
V
REF
V
REF
0.75
0.90
1.25
1.65
V
REF
V
REF
V
REF
V
REF
V
REF
0.6
0.75
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