XC3S1000-4FG676C

Manufacturer Part NumberXC3S1000-4FG676C
DescriptionFPGA Spartan®-3 Family 1M Gates 17280 Cells 630MHz 90nm Technology 1.2V 676-Pin FBGA
ManufacturerXilinx Inc
XC3S1000-4FG676C datasheets

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Specifications of XC3S1000-4FG676C

Package676FBGAFamily NameSpartan®-3
Device Logic Units17280Device System Gates1000000
Maximum Internal Frequency630 MHzTypical Operating Supply Voltage1.2 V
Maximum Number Of User I/os391Ram Bits442368
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Spartan-3 FPGA Family: DC and Switching Characteristics
Table 47: Test Methods for Timing Measurement at I/Os (Continued)
Signal Standard
(IOSTANDARD)
V
REF
DIFF_SSTL2_II
-
DIFF_SSTL2_II_DCI
Notes:
1.
Descriptions of the relevant symbols are as follows:
–
V
The reference voltage for setting the input switching threshold
REF
–
V
The common mode input voltage
ICM
–
V
Voltage of measurement point on signal transition
M
–
V
Low-level test voltage at Input pin
L
–
V
High-level test voltage at Input pin
H
–
R
Effective termination resistance, which takes on a value of 1M
T
–
V
Termination voltage
T
2.
The load capacitance (C
) at the Output pin is 0 pF for all signal standards.
L
3.
According to the PCI specification.
The capacitive load (C
) is connected between the output
L
and GND. The Output timing for all standards, as published
in the speed files and the data sheet, is always based on a
C
value of zero. High-impedance probes (less than 1 pF)
L
are used for all measurements. Any delay that the test fix-
ture might contribute to test measurements is subtracted
from those measurements to produce the final timing num-
bers as published in the speed files and data sheet.
Using IBIS Models to Simulate Load
Conditions in Application
IBIS Models permit the most accurate prediction of timing
delays for a given application. The parameters found in the
IBIS model (V
, R
, and V
REF
REF
MEAS
with the parameters used in
Table
not confuse V
(the termination voltage) from the IBIS
REF
model with V
(the input-switching threshold) from the
REF
table. A fourth parameter, C
, is always zero. The four
REF
parameters describe all relevant output test conditions. IBIS
78
Inputs
(V)
V
(V)
V
(V)
L
H
V
- 0.75
V
+ 0.75
ICM
ICM
Ω
models are found in the Xilinx development software as well
as at the following link.
http://www.xilinx.com/support/download/index.htm
Simulate delays for a given application according to its spe-
cific load conditions as follows:
1. Simulate the desired signal standard with the output
driver connected to the test setup shown in
Use parameter values V
C
REF
2. Record the time to V
3. Simulate the same signal standard with the output
driver connected to the PCB trace with load. Use the
) correspond directly
appropriate IBIS model (including V
47, V
, R
, and V
. Do
and V
T
T
M
load.
4. Record the time to V
5. Compare the results of steps 2 and 4. The increase (or
decrease) in delay should be added to (or subtracted
from) the appropriate Output standard adjustment
www.xilinx.com
Outputs
R
(Ω)
V
(V)
T
T
50
1.25
when no parallel termination is required
, R
, and V
from
T
T
M
is zero.
.
M
REF
values) or capacitive value to represent the
MEAS
.
MEAS
DS099-3 (v2.5) December 4, 2009
Product Specification
R
Inputs and
Outputs
V
(V)
M
V
ICM
Figure
33.
Table
47.
, R
, C
,
REF
REF

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