XC3S1000-4FG676C | |
|---|---|
| Manufacturer Part Number | XC3S1000-4FG676C |
| Description | FPGA Spartan®-3 Family 1M Gates 17280 Cells 630MHz 90nm Technology 1.2V 676-Pin FBGA |
| Manufacturer | Xilinx Inc |
| XC3S1000-4FG676C datasheets |
|
Availability: In stock
International delivery:
Warranty: 60 days
×
- We provide standard 60-days warranty for all parts. If warranty differs we always mention it beforehand. In case of return we cover shipping costs.
- If you still have any questions - please contact us
×
Shipping terms
- Standard delivery time differs from 5-8 business days if the supplier is a local one to 12-14 days if the suplier is from overseas. If delivery time differs it's always mentioned in our quotation.
- We ship worldwide using main international couriers like FedEx, DHL, UPS, TNT, EMS. We can also use client's freight account. Other shipping methods can be discussed. We do best to meet your needs!
Payment terms
- For new client payment term is payment in advance. At this moment we accept 3 payment methods: wire transfer, PayPal and Western Union. Credit card payment is under constrution and will be introduced soon. Escrow service is acceptable. Net terms for regular customers is not a problem. Working with us is totally safe for you.
- If you still have any questions - please contact us
Specifications of XC3S1000-4FG676C | |||
|---|---|---|---|
| Package | 676FBGA | Family Name | Spartan®-3 |
| Device Logic Units | 17280 | Device System Gates | 1000000 |
| Maximum Internal Frequency | 630 MHz | Typical Operating Supply Voltage | 1.2 V |
| Maximum Number Of User I/os | 391 | Ram Bits | 442368 |
PrevNext
Spartan-3 FPGA Family: DC and Switching Characteristics
Internal Logic Timing
Table 50: CLB Timing
Symbol
Clock-to-Output Times
T
When reading from the FFX (FFY) Flip-Flop,
CKO
the time from the active transition at the CLK
input to data appearing at the XQ (YQ) output
Setup Times
T
Time from the setup of data at the F or G input
AS
to the active transition at the CLK input of the
CLB
T
Time from the setup of data at the BX or BY
DICK
input to the active transition at the CLK input of
the CLB
Hold Times
T
Time from the active transition at the CLK input
AH
to the point where data is last held at the F or
G input
T
Time from the active transition at the CLK input
CKDI
to the point where data is last held at the BX or
BY input
Clock Timing
T
CLB CLK signal High pulse width
CH
T
CLB CLK signal Low pulse width
CL
F
Maximum toggle frequency (for export control)
TOG
Propagation Times
T
The time it takes for data to travel from the
ILO
CLB’s F (G) input to the X (Y) output
Set/Reset Pulse Width
T
The minimum allowable pulse width, High or
RPW_CLB
Low, to the CLB’s SR input
Notes:
1.
The numbers in this table are based on the operating conditions set forth in
2.
The timing shown is for SLICEM.
3.
For minimums, use the values reported by the Xilinx timing analyzer.
82
Description
Min
0.46
1.27
0.25
0.69
0.69
0.76
www.xilinx.com
Speed Grade
-5
-4
Max
Min
Max
-
0.63
-
0.72
-
0.53
-
-
1.57
-
0
-
0
-
-
0.29
-
∞
∞
0.79
∞
∞
0.79
-
725
-
630
-
0.53
-
0.61
-
0.87
-
Table
31.
DS099-3 (v2.5) December 4, 2009
Product Specification
R
Units
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
Related parts for XC3S1000-4FG676C | |||
|---|---|---|---|
| Part Number | Description | Manufacturer | Datasheet |
|
|
SPARTAN-3A FPGA 1M STD 256-FTBGA | Xilinx Inc | |
|
|
SPARTAN-3A FPGA 1M STD 456-FBGA | Xilinx Inc |
|
|
|
IC SPARTAN-3E FPGA 100K 144-TQFP | Xilinx Inc |
|
|
|
IC FPGA SPARTAN-3E 100K 144-TQFP | Xilinx Inc |
|
|
|
SPARTAN-3A FPGA 1M STD 676-FBGA | Xilinx Inc |
|
|
|
IC FPGA SPARTAN 3 256FTBGA | Xilinx Inc |
|
|
|
SEMI CONDUCTOR | Xilinx Inc |
|
|
|
FIELD PROGRAMMABLE GATE ARRAY | Xilinx Inc |
|
|
|
FIELD PROGRAMMER | Xilinx Inc |
|
|
|
FPGA Spartan®-3 Family 1M Gates 17280 Cells 630MHz 90nm Technology 1.2V 456-Pin FBGA | Xilinx Inc |
|
|
|
FPGA Spartan®-3 Family 1M Gates 17280 Cells 630MHz 90nm Technology 1.2V 676-Pin FBGA | Xilinx Inc |
|
|
|
FPGA Spartan®-3 Family 1M Gates 17280 Cells 630MHz 90nm Technology 1.2V 456-Pin FBGA | Xilinx Inc |
|
|
|
FPGA Spartan®-3 Family 1M Gates 17280 Cells 630MHz 90nm Technology 1.2V 256-Pin FTBGA | Xilinx Inc |
|
|
|
FPGA Spartan®-3 Family 1M Gates 17280 Cells 630MHz 90nm Technology 1.2V 256-Pin FTBGA | Xilinx Inc |
|
|
|
FPGA Spartan®-3E Family 100K Gates 2160 Cells 572MHz 90nm (CMOS) Technology 1.2V 100-Pin VTQFP | Xilinx Inc |
|
