XC3S1000-4FG676C

Manufacturer Part NumberXC3S1000-4FG676C
DescriptionFPGA Spartan®-3 Family 1M Gates 17280 Cells 630MHz 90nm Technology 1.2V 676-Pin FBGA
ManufacturerXilinx Inc
XC3S1000-4FG676C datasheets

Availability: In stock

International delivery:

Warranty: 60 days

Shipping & payment terms

Added to cart

 

Specifications of XC3S1000-4FG676C

Package676FBGAFamily NameSpartan®-3
Device Logic Units17280Device System Gates1000000
Maximum Internal Frequency630 MHzTypical Operating Supply Voltage1.2 V
Maximum Number Of User I/os391Ram Bits442368
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
Page 81
82
Page 82
83
Page 83
84
Page 84
85
Page 85
86
Page 86
87
Page 87
88
Page 88
89
Page 89
90
Page 90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
Page 82/217

Download datasheet (6Mb)Embed
PrevNext
Spartan-3 FPGA Family: DC and Switching Characteristics
Internal Logic Timing
Table 50: CLB Timing
Symbol
Clock-to-Output Times
T
When reading from the FFX (FFY) Flip-Flop,
CKO
the time from the active transition at the CLK
input to data appearing at the XQ (YQ) output
Setup Times
T
Time from the setup of data at the F or G input
AS
to the active transition at the CLK input of the
CLB
T
Time from the setup of data at the BX or BY
DICK
input to the active transition at the CLK input of
the CLB
Hold Times
T
Time from the active transition at the CLK input
AH
to the point where data is last held at the F or
G input
T
Time from the active transition at the CLK input
CKDI
to the point where data is last held at the BX or
BY input
Clock Timing
T
CLB CLK signal High pulse width
CH
T
CLB CLK signal Low pulse width
CL
F
Maximum toggle frequency (for export control)
TOG
Propagation Times
T
The time it takes for data to travel from the
ILO
CLB’s F (G) input to the X (Y) output
Set/Reset Pulse Width
T
The minimum allowable pulse width, High or
RPW_CLB
Low, to the CLB’s SR input
Notes:
1.
The numbers in this table are based on the operating conditions set forth in
2.
The timing shown is for SLICEM.
3.
For minimums, use the values reported by the Xilinx timing analyzer.
82
Description
Min
0.46
1.27
0.25
0.69
0.69
0.76
www.xilinx.com
Speed Grade
-5
-4
Max
Min
Max
-
0.63
-
0.72
-
0.53
-
-
1.57
-
0
-
0
-
-
0.29
-
0.79
0.79
-
725
-
630
-
0.53
-
0.61
-
0.87
-
Table
31.
DS099-3 (v2.5) December 4, 2009
Product Specification
R
Units
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns