XC3S1000-4FG676C | |
|---|---|
| Manufacturer Part Number | XC3S1000-4FG676C |
| Description | FPGA Spartan®-3 Family 1M Gates 17280 Cells 630MHz 90nm Technology 1.2V 676-Pin FBGA |
| Manufacturer | Xilinx Inc |
| XC3S1000-4FG676C datasheets |
|
Availability: In stock
International delivery:
Warranty: 60 days
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Specifications of XC3S1000-4FG676C | |||
|---|---|---|---|
| Package | 676FBGA | Family Name | Spartan®-3 |
| Device Logic Units | 17280 | Device System Gates | 1000000 |
| Maximum Internal Frequency | 630 MHz | Typical Operating Supply Voltage | 1.2 V |
| Maximum Number Of User I/os | 391 | Ram Bits | 442368 |
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PrevNext
Spartan-3 FPGA Family: DC and Switching Characteristics
Phase Shifter (PS)
Phase shifter operation is only supported if the DLL is in low-frequency mode, see
software version 10.1.03 (or later).
Table 61: Recommended Operating Conditions for the PS in Variable Phase Mode
Symbol
Description
Operating Frequency Ranges
PSCLK_FREQ
Frequency for the
(F
)
PSCLK input
PSCLK
Input Pulse Requirements
PSCLK_PULSE
PSCLK pulse width
as a percentage of
the PSCLK period
Table 62: Switching Characteristics for the PS in Variable or Fixed Phase Shift Mode
Symbol
Description
Phase Shifting Range
FINE_SHIFT_RANGE
Phase shift range
Lock Time
LOCK_DLL_PS
When using the PS in conjunction
with the DLL: The time from
deassertion at the DCM’s Reset
input to the rising transition at its
LOCKED output. When the DCM
is locked, the CLKIN and CLKFB
signals are in phase.
LOCK_DLL_PS_FX
When using the PS in conjunction
with the DLL and DFS: The time
from deassertion at the DCM’s
Reset input to the rising transition
at its LOCKED output. When the
DCM is locked, the CLKIN and
CLKFB signals are in phase.
Notes:
1.
The numbers in this table are based on the operating conditions set forth in
2.
The PS specifications in this table apply when the PS attribute CLKOUT_PHASE_SHIFT= VARIABLE or FIXED.
90
Frequency Mode/
F
Range
Min
CLKIN
Low
1
Low
F
< 100 MHz
40%
CLKIN
F
> 100 MHz
45%
CLKIN
Frequency Mode/
F
Range
CLKIN
Low
18 MHz < F
< 30 MHz
CLKIN
30 MHz < F
< 40 MHz
CLKIN
40 MHz < F
< 50 MHz
CLKIN
50 MHz < F
< 60 MHz
CLKIN
60 MHz < F
< 165 MHz
CLKIN
Low
Table 31
www.xilinx.com
Table
57. Fixed phase shift requires ISE
Speed Grade
-5
-4
Max
Min
Max
167
1
167
60%
40%
60%
55%
45%
55%
Speed Grade
-5
-4
Min
Max
Min
Max
-
10.0
-
10.0
-
3.28
-
3.28
-
2.56
-
2.56
-
1.60
-
1.60
-
1.00
-
1.00
-
0.88
-
0.88
-
10.40
-
10.40
and
Table
61.
DS099-3 (v2.5) December 4, 2009
Product Specification
R
Units
MHz
-
-
Units
ns
ms
ms
ms
ms
ms
ms
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