XC3S1000-4FG676C

Manufacturer Part NumberXC3S1000-4FG676C
DescriptionFPGA Spartan®-3 Family 1M Gates 17280 Cells 630MHz 90nm Technology 1.2V 676-Pin FBGA
ManufacturerXilinx Inc
XC3S1000-4FG676C datasheets

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Specifications of XC3S1000-4FG676C

Package676FBGAFamily NameSpartan®-3
Device Logic Units17280Device System Gates1000000
Maximum Internal Frequency630 MHzTypical Operating Supply Voltage1.2 V
Maximum Number Of User I/os391Ram Bits442368
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R
Revision History
Date
Version No.
04/11/03
1.0
Initial Xilinx release.
07/11/03
1.1
Extended Absolute Maximum Rating for junction temperature in
quiescent supply current
02/06/04
1.2
Revised V
number
current numbers
LVDCI_DV2 and LVPECL standards
Table
66).
03/04/04
1.3
Added timing numbers from v1.29 speed files as well as DCM timing
08/24/04
1.4
Added reference to errata documents on
information
(Table
32). Updated quiescent current numbers and added information on power-on and surplus current
(Table
33). Adjusted V
(Table
34). Added note limiting V
V
levels for differential standards
OL
(Table 39
Updated DCM timing with latest characterization data
pulse width specification
Improved DCM PSCLK pulse width specification
(Table
62). Because the BitGen option Centered_x#_y# is not necessary for Variable Phase Shift mode,
removed BitGen command table and referring text. Adjusted maximum CCLK frequency for the slave
serial and parallel configuration modes
setup times
12/17/04
1.5
Updated timing parameters to match v1.35 speed file. Improved V
Added a note limiting the rate of change of V
the XC3S2000, XC3S4000, and XC3S5000
standards
guidelines for the FT and FG packages
using compressed bitstreams
(Table
34,
08/19/05
1.6
Updated timing parameters to match v1.37 speed file. All Spartan-3 part types, except XC3S5000,
promoted to Production status. Removed V
devices
(Table
32). Added worst-case quiescent current values for XC3S2000, XC3S4000, XC3S5000
(Table
33). Added industrial temperature range specification and improved typical quiescent current
values
18 MHz
(Table
59,
Industrial temperature range applications. Updated
Table 49
SDRAM interfaces. Added differential (or complementary single-ended) DIFF_HSTL_II_18 and
DIFF_SSTL2_II I/O standards, including DCI terminated versions. Added electro-static discharge (ESD)
data for the XC3S2000 and larger FPGAs
receive automatic notifications of data sheet or errata changes.
04/03/06
2.0
Upgraded Module 3, removing Preliminary status. Moved XC3S5000 to Production status in
Finalized I/O timing on XC3S5000 for v1.38 speed files. Added minimum timing values for various logic
and I/O paths. Corrected labels for R
mask revision ‘E’ specifications for LVDS_25, RSDS_25, LVDSEXT_25 differential outputs to
Added BLVDS termination requirements to
Outputs (SSOs) limits in
on a printed circuit board. Updated Note 2 in
minimum pulse width specification, T
DS099-3 (v2.5) December 4, 2009
Product Specification
98
Spartan-3 FPGA Family: DC and Switching Characteristics
Description
(Table
33) and DLL timing.
maximum rating
(Table
27). Added power-on requirements
IN
(Table
32), and differential output voltage levels
(Table
33). Updated pull-up and pull-down resistor strengths
(Table 36
page
(Table
27). Explained V
ramp time measurement
CCO
range for HSTL_III and HSTL_I_18 and changed V
REF
range for SSTL2_II signal standards
TT
(Table
37). Updated Switching Characteristics with speed file v1.32
through
Table 47
and
Table 50
through
(Table
57). Recommended use of Virtex-II FPGA Jitter calculator
(Table
65). Inverted CCLK waveform
(Table
67).
CCAUX
(Table
(Table
35). Added SSO guidelines for the VQ, TQ, and PQ packages as well as edited SSO
(Table
49). Added maximum CCLK frequencies for configuration
(Table 65
and
Table
Table
35,
Table
43,
Table
46,
Table
47, and
CCO
(Table
29). Added equivalent resistance values for internal pull-up and pull-down resistors
(Table
33). Improved the DLL minimum clock input frequency specification from 24 MHz down to
(Table
57). Improved the DFS minimum and maximum clock output frequency specifications
Table
60). Added new miscellaneous DCM specifications
for QFP packages. Added information on SSTL18_II I/O standard and timing to support DDR2
(Table
and R
PU
PD
Figure
Table 49
for quad-flat packaged based on silicon testing using devices soldered
Table
, to
Table
INIT
www.xilinx.com
Table
27. Added numbers for typical
(Table
29), leakage current
(Table
37) for Rev. 0. Published new quiescent
(Table
32). Added
and
Table
37). Changed CCLK setup time
(Table 57
through
55. Clarified Absolute Maximum Ratings and added ESD
(Table
29). Clarified I
min for LVCMOS12
IH
(Table
35). Calculated V
Table
55). Corrected IOB test conditions
(Table 57
through
Table
61). Improved DCM CLKIN
(Table
61). Changed Phase Shifter lock time parameter
(Figure
35). Adjusted JTAG
ramp time specification
CCO
(Table
31). Added typical quiescent current values for
33). Increased I
and I
for SSTL2-I and SSTL2-II
OH
OL
66). Added specifications for the HSLVDCI standards
Table
49).
ramp rate restriction from all mask revision ‘E’ and later
(Table
63), primarily affecting
Simultaneously Switching Output Guidelines
27). Added link to Spartan-3 errata notices and how to
and updated R
conditions for in
Table
PD
32. Improved recommended Simultaneous Switching
62. Updated Note 6 in
Table
29. Added INIT_B
64.
(Table 65
and
Table
62).
specification
L
and
OH
(Table
40).
(Table
60).
(Table
29).
and
Table
38.
32. Added final
Table
37.
97

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