XC3S1000-4FG676C | |
|---|---|
| Manufacturer Part Number | XC3S1000-4FG676C |
| Description | FPGA Spartan®-3 Family 1M Gates 17280 Cells 630MHz 90nm Technology 1.2V 676-Pin FBGA |
| Manufacturer | Xilinx Inc |
| XC3S1000-4FG676C datasheets |
|
Availability: In stock
International delivery:
Warranty: 60 days
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Specifications of XC3S1000-4FG676C | |||
|---|---|---|---|
| Package | 676FBGA | Family Name | Spartan®-3 |
| Device Logic Units | 17280 | Device System Gates | 1000000 |
| Maximum Internal Frequency | 630 MHz | Typical Operating Supply Voltage | 1.2 V |
| Maximum Number Of User I/os | 391 | Ram Bits | 442368 |
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PrevNext
Spartan-3 FPGA Family: DC and Switching Characteristics
Date
Version No.
04/26/06
2.1
Updated document links.
05/25/07
2.2
Improved absolute maximum voltage specifications in
allowance. Improved XC3S50 HBM ESD to 2000V in
data, improved (reduced) the maximum quiescent current limits for the I
in
Table
footnote in
in
Table
11/30/07
2.3
Updated 3.3V VCCO max from 3.45V to 3.465V in
0.50μs to 0.25μs in
06/25/08
2.4
Clarified dual marking. Added
Table
31. Removed absolute minimum and added footnote referring to timing analyzer for minimum delay
values. Added HSLVDCI to
value in speed file. Updated formatting and links.
12/04/09
2.5
Updated notes 2 and 3 in
Table
29. Updated note 3 in
V
max and V
OL
in
Figure
Table
47. Updated
being discontinued in
Updated footnote 3 in
Removed silicon process specific information and revised notes in
(PS).
98
Description
33. Widened the recommended voltage range for the PCI standard and clarified the hysteresis
Table
34. Noted restriction on combining differential outputs in
63.
Table
64. Updated links to technical documentation.
Mask and Fab
Revisions. Added references to
Table 47
and
Table
49. Updated t
Table
27. Removed silicon process specific information and revised notes in
Table
31. Updated note 3 in
min for SSTL2_II in
Table
35. Updated note 5 in
OH
37. Updated V
max for LVPECL_25 in
ICM
Simultaneously Switching Output
Table
48. Removed minimum values for T
Table
57. Removed minimum values for T
www.xilinx.com
Table
27, providing additional overshoot
Table
27. Based on extensive 90 nm production
and I
CCINTQ
CCOQ
Table
37. Updated footnote 1
Table 31
and elsewhere. Reduced t
ICCK
XAPP459
in
in
Table 50
to match largest possible
DICK
Table
33. Updated note 5 in
Table
Table
35. Updated JTAG Waveforms
Table
36. Updated RT and VT for LVDS_25_DCI in
Guidelines. Noted that the CP132 package is
clock-to-output times in
MULTCK
propagation times in
MULT
Table
60. Updated
Phase Shifter
DS099-3 (v2.5) December 4, 2009
Product Specification
R
specifications
minimum from
Table 27
and
34. Updated
Table
53.
Table
54.
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