XC3S1400A-5FTG256C Xilinx Inc, XC3S1400A-5FTG256C Datasheet

FPGA Spartan®-3A Family 1.4M Gates 25344 Cells 770MHz 90nm Technology 1.2V 256-Pin FTBGA

XC3S1400A-5FTG256C

Manufacturer Part Number
XC3S1400A-5FTG256C
Description
FPGA Spartan®-3A Family 1.4M Gates 25344 Cells 770MHz 90nm Technology 1.2V 256-Pin FTBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3Ar

Specifications of XC3S1400A-5FTG256C

Package
256FTBGA
Family Name
Spartan®-3A
Device Logic Units
25344
Device System Gates
1400000
Maximum Internal Frequency
770 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
161
Ram Bits
589824
Number Of Logic Elements/cells
25344
Number Of Labs/clbs
2816
Total Ram Bits
589824
Number Of I /o
161
Number Of Gates
1400000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-LBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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0
The Programmable Logic
Challenge of I/O Intensive
Designs
The Xilinx FPGA Solution
Traditional FPGAs are proportionate
between logic and I/O not being cost-
effective for I/O intensive designs
to fast-evolving I/O standards
require low-cost and robust security
solutions
The Spartan
for applications where I/O count and
capabilities matter more than logic density
The Spartan-3A platform delivers up to
502 I/Os with support for industry-leading
26 popular and emerging I/O standards
The industry’s first 90nm FPGA electronic
ID - Device DNA serial number provides
a cost-effective, robust mechanism to help
protect against reverse-engineering,
cloning and overbuilding
System designers need to quickly adapt
High volume consumer applications
-3A FPGAs were designed
Xilinx Spartan
The World’s Lowest-Cost I/O Optimized FPGAs
Xilinx is driving the multiple domain-optimized platforms for highly efficient and
optimal design solutions, instead of forcing inefficient, one-size-fits-all solutions on
significantly varying application requirements.
Spartan-3A Platform Key Features
Standard Low-Cost Features
The Spartan-3A FPGA platform is a full feature platform of five devices with
system gates ranging from 50K to 1.4M gates, and I/Os ranging from 108 to 502
I/Os, with density migration. The Spartan-3A FPGAs also support up to 576 Kbits of
fast-block RAM with byte-write enable, and up to 176 Kbits of distributed RAM.
Additionally, there are built-in multipliers for efficient DSP implementation and
Digital Clock Managers (DCMs) for system level clock management functions.
Advance Features
The advance features in the Spartan-3A platform include unique Device DNA
serial number, support for 26 I/O standards, enhanced Multi-Boot capability
with watchdog timer, dual power management modes, and Dynamic Input
Delay for precise data-to-clock centering. These advance features significantly
help shorten design cycles and lower system cost.
-3A FPGA Platform
SPARTAN-3 GENERATION FPGAs

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XC3S1400A-5FTG256C Summary of contents

Page 1

Xilinx Spartan The Programmable Logic Challenge of I/O Intensive Designs • Traditional FPGAs are proportionate between logic and I/O not being cost- effective for I/O intensive designs • System designers need to quickly adapt to fast-evolving I/O standards • High ...

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... XC3S1400A 375 502 www.xilinx.com Copyright © 2OO7 Xilinx, Inc. All rights reserved. XILINX, the Xilinx Logo, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners Printed in U.S.A. PN 2010 ...

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