XC5VSX50T-1FFG665I Xilinx Inc, XC5VSX50T-1FFG665I Datasheet - Page 23

• Manufacturer Part Number: XC5VSX50T-1FFG665I
• Description: FPGA Virtex®-5 Family 52224 Cells 65nm (CMOS) Technology 1V 665-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 SXTr

Specifications of XC5VSX50T-1FFG665I

• Package: 665FCBGA
• Family Name: Virtex®-5
• Device Logic Units: 52224
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 360
• Ram Bits: 4866048
• Number Of Logic Elements/cells: 52224
• Number Of Labs/clbs: 4080
• Total Ram Bits: 4866048
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 665-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 45: GTX_DUAL Tile User Clock Switching Characteristics
Table 46: GTX_DUAL Tile Transmitter Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
Notes:
1.
Symbol
F
F
TXOUT
RXREC
T
T
T
T
T
RX2
TX2
Clocking must be implemented as described in UG198: Virtex-5 FPGA RocketIO GTX Transceiver User Guide.
RX
TX
TXOOBTRANSITION
V
TXOOBVDPP
T
Symbol
F
D
LLSKEW
T
T
T
T
D
T
D
GTXTX
J4.25
TXOUTCLK maximum frequency
RXRECCLK maximum frequency
RXUSRCLK maximum frequency
RXUSRCLK2 maximum frequency
TXUSRCLK maximum frequency
TXUSRCLK2 maximum frequency
J4.25
RTX
FTX
J6.5
J5.0
J6.5
J5.0
Description
Serial data rate range
TX Rise time
TX Fall time
TX lane-to-lane skew
Electrical idle amplitude
Electrical idle transition time
Total Jitter
Deterministic Jitter
Total Jitter
Deterministic Jitter
Total Jitter
Deterministic Jitter
(2)
(2)
(2)
Description
(2)
(2)
(2)
(1)
Internal 20-bit datapath
Internal 16-bit datapath
1 byte interface
2 byte interface
4 byte interface
1 byte interface
2 byte interface
4 byte interface
1 byte interface
2 byte interface
4 byte interface
1 byte interface
2 byte interface
4 byte interface
Conditions
www.xilinx.com
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Condition
20%–80%
80%–20%
4.25 Gb/s
6.5 Gb/s
5.0 Gb/s
(1)
Device
FXT
FXT
FXT
FXT
TXT
FXT
FXT
TXT
TXT
FXT
TXT
TXT
TXT
TXT
203.125
203.125
406.25
406.25
406.25
406.25
406.25
406.25
0.15
Min
325
375
375
-3
-
-
-
-
-
-
-
-
-
-
-
Speed Grade
390.625
203.125
265.625
203.125
390.625
203.125
265.625
203.125
406.25
406.25
406.25
406.25
406.25
406.25
406.25
406.25
312.5
312.5
312.5
312.5
Typ
120
120
325
325
-2
F
265.625
265.625
265.625
265.625
265.625
265.625
235.625
265.625
132.813
235.625
265.625
132.813
265.625
265.625
235.625
265.625
132.813
235.625
265.625
132.813
GTXMAX
212.5
212.5
Max
0.33
0.17
0.33
0.15
0.33
0.14
350
15
75
-1
Units
Units
Gb/s
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
mV
ps
ps
ps
ns
UI
UI
UI
UI
UI
UI
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