LFE3-150EA-7FN672C LATTICE SEMICONDUCTOR, LFE3-150EA-7FN672C Datasheet

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LatticeECP3 Family Data Sheet DS1021 Version 01.9EA, July 2011 ...

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... Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...

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... Lattice Semiconductor Introduction The LatticeECP3™ (EConomy Plus Third generation) family of FPGA devices is optimized to deliver high perfor- mance features such as an enhanced DSP architecture, high speed SERDES and high speed source synchronous interfaces in an economical FPGA fabric. This combination is achieved through advances in device architecture and the use of 65nm technology making the devices suitable for high-volume, high-speed, low-cost applications ...

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... The LatticeECP3 devices use 1.2V as their core voltage. © 2011 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...

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... Lattice Semiconductor Figure 2-1. Simplified Block Diagram, LatticeECP3-35 Device (Top Level) JTAG sysIO Bank 7 Enhanced DSP Slices: Multiply, Accumulate and ALU sysCLOCK PLLs & DLLs: Frequency Synthesis and Clock Alignment sysMEM Block RAM: 18Kbit Programmable Function Units 149K LUTs sysIO Bank 6 Note: There is no Bank 4 or Bank 5 in LatticeECP3 devices ...

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... Lattice Semiconductor Figure 2-2. PFU Diagram LUT4 & LUT4 & CARRY CARRY Slice Slice Slice 0 through Slice 2 contain two LUT4s feeding two registers, whereas Slice 3 contains two LUT4s only. For PFUs, Slice 0 through Slice 2 can be configured as distributed memory, a capability not available in the PFF. ...

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... Lattice Semiconductor Figure 2-3. Slice Diagram FXB FXA From Routing CLK LSR * Not in Slice 3 For Slices 0 and 1, memory control signals are generated from Slice 2 as follows: Table 2-2. Slice Signal Descriptions Function Type Input Data signal Input Data signal Input Multi-purpose ...

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... Lattice Semiconductor Modes of Operation Each slice has up to four potential modes of operation: Logic, Ripple, RAM and ROM. Logic Mode In this mode, the LUTs in each slice are configured as 4-input combinatorial lookup tables. A LUT4 can have 16 possible input combinations. Any four input logic functions can be generated by programming this lookup table. ...

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... Lattice Semiconductor ROM Mode ROM mode uses the LUT logic; hence, Slices 0 through 3 can be used in ROM mode. Preloading is accomplished through the programming interface during PFU configuration. For more information, please refer to TN1179, Routing There are many resources provided in the LatticeECP3 devices to route signals individually or as busses with related control signals ...

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... Lattice Semiconductor Figure 2-4. General Purpose PLL Diagram FDA[3:0] WRDEL CLKI CLKI Divider CLKFB CLKFB Divider RSTK RST DRPAI[3:0] DFPAI[3:0] Table 2-4 provides a description of the signals in the PLL blocks. Table 2-4. PLL Blocks Signal Descriptions Signal I/O CLKI I Clock input from external pin or routing ...

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... Lattice Semiconductor chain in order to better match the reference and feedback signals. This digital code from the ALU is also transmit- ted via the Digital Control bus (DCNTL) bus to its associated Slave Delay lines (two per DLL). The ALUHOLD input allows the user to suspend the ALU output at its current value. The UDDCNTL signal allows the user to latch the current value on the DCNTL bus ...

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... Lattice Semiconductor Table 2-5. DLL Signals Signal I/O CLKI I Clock input from external pin or routing CLKFB I DLL feed input from DLL output, clock net, routing or external pin RSTN I Active low synchronous reset ALUHOLD I Active high freezes the ALU UDDCNTL I Synchronous enable signal (hold high for two cycles) from routing ...

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... Lattice Semiconductor PLL/DLL Cascading LatticeECP3 devices have been designed to allow certain combinations of PLL and DLL cascading. The allowable combinations are: • PLL to PLL supported • PLL to DLL supported The DLLs in the LatticeECP3 are used to shift the clock in relation to the data for source synchronous inputs. PLLs are used for frequency synthesis and clock generation for source synchronous interfaces ...

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... Lattice Semiconductor Figure 2-8. Clock Divider Connections CLKOP (PLL) CLKOP (DLL) Clock Distribution Network LatticeECP3 devices have eight quadrant-based primary clocks and eight secondary clock/control sources. Two high performance edge clocks are available on the top, left, and right edges of the device to support high speed interfaces ...

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... Lattice Semiconductor Figure 2-10. Primary Clock Sources for LatticeECP3-35 PLL Input Clock Input Clock Input DLL Input PLL Input Figure 2-11. Primary Clock Sources for LatticeECP3-70, -95, -150 PLL Input PLL Input Clock Input Clock Input DLL Input PLL Input PLL Input ...

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... Lattice Semiconductor Primary Clock Routing The purpose of the primary clock routing is to distribute primary clock sources to the destination quadrants of the device. A global primary clock is a primary clock that is distributed to all quadrants. The clock routing structure in LatticeECP3 devices consists of a network of eight primary clock lines (CLK0 through CLK7) per quadrant. The pri- mary clocks of each quadrant are generated from muxes located in the center of the device ...

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... Lattice Semiconductor Secondary Clock/Control Sources LatticeECP3 devices derive eight secondary clock sources (SC0 through SC7) from six dedicated clock input pads and the rest from routing. Figure 2-14 shows the secondary clock sources. All eight secondary clock sources are defined as inputs to a per-region mux SC0-SC7. SC0-SC3 are primary for control signals (CE and/or LSR), and SC4-SC7 are for the clock ...

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... Lattice Semiconductor Table 2-6. Secondary Clock Regions Figure 2-15. LatticeECP3-70 and LatticeECP3-95 Secondary Clock Regions sysIO Bank 0 Secondary Clock Region R1C1 Secondary Clock Region R2C1 Secondary Clock Region R3C1 Secondary Clock Region R4C1 Secondary Clock Region R5C1 Number of Secondary Clock Device ...

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... Lattice Semiconductor Figure 2-16. Per Region Secondary Clock Selection 8:1 8:1 SC0 SC1 Slice Clock Selection Figure 2-17 shows the clock selections and Figure 2-18 shows the control selections for Slice0 through Slice2. All the primary clocks and seven secondary clocks are routed to this clock selection mux. Other signals can be used as a clock input to the slices via routing ...

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... Lattice Semiconductor Edge Clock Sources Edge clock resources can be driven from a variety of sources at the same edge. Edge clock resources can be driven from adjacent edge clock PIOs, primary clock PIOs, PLLs, DLLs, Slave Delay and clock dividers as shown in Figure 2-19. Figure 2-19. Edge Clock Sources ...

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... Lattice Semiconductor Figure 2-20. Sources of Edge Clock (Left and Right Edges) Figure 2-21. Sources of Edge Clock (Top Edge) The edge clocks have low injection delay and low skew. They are used to clock the I/O registers and thus are ideal for creating I/O interfaces with a single clock signal and a wide data bus. They are also used for DDR Memory or Generic DDR interfaces ...

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... Lattice Semiconductor The edge clocks on the top, left, and right sides of the device can drive the secondary clocks or general routing resources of the device. The left and right side edge clocks also can drive the primary clock network through the clock dividers (CLKDIV). ...

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... Lattice Semiconductor Single, Dual and Pseudo-Dual Port Modes In all the sysMEM RAM modes the input data and address for the ports are registered at the input of the memory array. The output data of the memory is optionally registered at the output. EBR memory supports the following forms of write behavior for single port or dual port operation: 1. Normal – ...

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... Lattice Semiconductor This allows designers to use highly parallel implementations of DSP functions. Designers can optimize DSP perfor- mance vs. area by choosing appropriate levels of parallelism. Figure 2-23 compares the fully serial implementation to the mixed parallel and serial implementation. Figure 2-23. Comparison of General DSP and LatticeECP3 Approaches ...

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... Lattice Semiconductor as, overflow, underflow and convergent rounding, etc. – Flexible cascading across slices to get larger functions • RTL Synthesis friendly synchronous reset on all registers, while still supporting asynchronous reset for legacy users • Dynamic MUX selection to allow Time Division Multiplexing (TDM) of resources for applications that require ...

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... Lattice Semiconductor Figure 2-25. Detailed sysDSP Slice Diagram C SRIB SRIA IR Previous DSP Slice C_ALU CIN A_ALU Rounding Input Register PR = Pipeline Register OR = Output Register FR = Flag Register Note: A_ALU, B_ALU and C_ALU are internal signals generated by combining bits from AA, AB and C inputs. See TN1182, LatticeECP3 sysDSP Usage Guide, for further information. ...

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... Lattice Semiconductor For further information, please refer to TN1182, MULT DSP Element This multiplier element implements a multiply with no addition or accumulator nodes. The two operands, AA and AB, are multiplied and the result is available at the output. The user can enable the input/output and pipeline regis- ters ...

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... Lattice Semiconductor MAC DSP Element In this case, the two operands, AA and AB, are multiplied and the result is added with the previous accumulated value. This accumulated value is available at the output. The user can enable the input and pipeline registers, but the output register is always enabled. The output register is used to store the accumulated value. The ALU is con- figured as the accumulator in the sysDSP slice in the LatticeECP3 family can be initialized dynamically ...

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... Lattice Semiconductor MMAC DSP Element The LatticeECP3 supports a MAC with two multipliers. This is called Multiply Multiply Accumulate or MMAC. In this case, the two operands, AA and AB, are multiplied and the result is added with the previous accumulated value and with the result of the multiplier operation of operands BA and BB. This accumulated value is available at the output. ...

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... Lattice Semiconductor MULTADDSUB DSP Element In this case, the operands AA and AB are multiplied and the result is added/subtracted with the result of the multi- plier operation of operands BA and BB. The user can enable the input, output and pipeline registers. Figure 2-29 shows the MULTADDSUB sysDSP element. ...

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... Lattice Semiconductor MULTADDSUBSUM DSP Element In this case, the operands AA and AB are multiplied and the result is added/subtracted with the result of the multi- plier operation of operands BA and BB of Slice 0. Additionally, the operands AA and AB are multiplied and the result is added/subtracted with the result of the multiplier operation of operands BA and BB of Slice 1. The results of both addition/subtractions are added by the second ALU following the slice cascade path ...

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... Lattice Semiconductor Figure 2-31. MULTADDSUBSUM Slice 1 C SRIB SRIA IR Previous DSP Slice C_ALU CIN A_ALU Rounding Input Register PR = Pipeline Register OR = Output Register FR = Flag Register Advanced sysDSP Slice Features Cascading The LatticeECP3 sysDSP slice has been enhanced to allow cascading. Adder trees are implemented fully in sys- DSP slices, improving the performance ...

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... Lattice Semiconductor ALU Flags The sysDSP slice provides a number of flags from the ALU including: • Equal to zero (EQZ) • Equal to zero with mask (EQZM) • Equal to one with mask (EQOM) • Equal to pattern with mask (EQPAT) • Equal to bit inverted pattern with mask (EQPATB) • ...

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... Lattice Semiconductor Programmable I/O Cells (PIC) Each PIC contains two PIOs connected to their respective sysI/O buffers as shown in Figure 2-32. The PIO Block supplies the output data (DO) and the tri-state control signal (TO) to the sysI/O buffer and receives input from the buffer. Table 2-11 provides the PIO signal list. ...

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... Lattice Semiconductor Two adjacent PIOs can be joined to provide a differential I/O pair (labeled as “T” and “C”) as shown in Figure 2-32. The PAD Labels “T” and “C” distinguish the two PIOs. Approximately 50% of the PIO pairs on the left and right edges of the device can be configured as true LVDS outputs ...

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... Lattice Semiconductor Input signals are fed from the sysI/O buffer to the input register block (as signal DI). If desired, the input signal can bypass the register and delay elements and be used directly as a combinatorial signal (INDD), a clock (INCK) and, in selected blocks, the input to the DQS delay block input delay is desired, designers can select either a fixed delay or a dynamic delay DEL[3:0] ...

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... Lattice Semiconductor Figure 2-33. Input Register Block for Left, Right and Top Edges INCLK** INDD To DQSI** Fixed Delay DI Dynamic Delay (From sysIO Buffer) DEL[3:0] ECLKDQSR ECLK2 DDRCLKPOL ECLK1 1 ECLK2 0 SCLK * Only on the left and right sides. ** Selected PIO. Note: Simplified diagram does not show CE/SET/REST details. ...

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... Lattice Semiconductor Figure 2-34. Output and Tristate Block for Left and Right Edges TS OPOSA ONEGA OPOSB ONEGB Clock Transfer Registers SCLK DQCLK1 DQCLK0 Tristate Register Block The tristate register block registers tri-state control signals from the core of the device before they are passed to the sysI/O buffers ...

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... Lattice Semiconductor Control Logic Block The control logic block allows the selection and modification of control signals for use in the PIO block. DDR Memory Support Certain PICs have additional circuitry to allow the implementation of high-speed source synchronous and DDR, DDR2 and DDR3 memory interfaces. The support varies by the edge of the device as detailed below. ...

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... Lattice Semiconductor (referred to as DQS) is not free-running so this approach cannot be used. The DQS Delay block provides the required clock alignment for DDR memory interfaces. The delay required for the DQS signal is generated by two dedicated DLLs (DDR DLL) on opposite side of the device. Each DLL creates DQS delays in its half of the device as shown in Figure 2-36. The DDR DLL on the left side will generate delays for all the DQS Strobe pins on Banks 0, 7 and 6 and DDR DLL on the right will generate delays for all the DQS pins on Banks 1, 2 and 3 ...

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... Lattice Semiconductor Figure 2-36. Edge Clock, DLL Calibration and DQS Local Bus Distribution Bank 0 DQS DQS DQS DQS DDR DLL (Left) DQS Strobe and Transition Detect Logic I/O Ring *Includes shared configuration I/Os and dedicated configuration I/Os. Bank 1 DQS DQS DQS ...

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... Lattice Semiconductor Figure 2-37. DQS Local Bus Polarity Control Logic In a typical DDR Memory interface design, the phase relationship between the incoming delayed DQS strobe and the internal system clock (during the READ cycle) is unknown. The LatticeECP3 family contains dedicated circuits to transfer data between these domains ...

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... Lattice Semiconductor To accomplish write leveling in DDR3, each DQS group has a slightly different delay that is set by DYN DELAY[7:0] in the DQS Write Control logic block. The DYN DELAY can set 128 possible delay step settings. In addition, the most significant bit will invert the clock for a 180-degree shift of the incoming clock. ...

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... Lattice Semiconductor Figure 2-38. LatticeECP3 Banks V REF1(7) V REF2(7) V CCIO7 GND V REF1(6) V REF2(6) V CCIO6 GND LatticeECP3 devices contain two types of sysI/O buffer pairs. 1. Top (Bank 0 and Bank 1) and Bottom sysIO Buffer Pairs (Single-Ended Outputs Only) The sysI/O buffer pairs in the top banks of the device consist of two single-ended output drivers and two sets of single-ended input buffers (both ratioed and referenced). One of the referenced input buffers can also be con- figured as a differential input. Only the top edge buffers have a programmable PCI clamp. ...

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... Lattice Semiconductor 2. Left and Right (Banks and 7) sysI/O Buffer Pairs (50% Differential and 100% Single-Ended Out- puts) The sysI/O buffer pairs in the left and right banks of the device consist of two single-ended output drivers, two sets of single-ended input buffers (both ratioed and referenced) and one differential output driver. One of the referenced input buffers can also be configured as a differential input. In these banks the two pads in the pair are described as “ ...

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... Lattice Semiconductor On-Chip Programmable Termination The LatticeECP3 supports a variety of programmable on-chip terminations options, including: • Dynamically switchable Single-Ended Termination with programmable resistor values of 40, 50 ohms. External termination to Vtt should be used for DDR2 and DDR3 memory controller implementation. • Common mode termination of 80, 100, 120 ohms for differential inputs Figure 2-39 ...

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... Lattice Semiconductor Please see TN1177, LatticeECP3 sysIO Usage Guide Equalization Filter Equalization filtering is available for single-ended inputs on both true and complementary I/Os, and for differential inputs on the true I/Os on the left, right, and top sides. Equalization is required to compensate for the difficulty of sampling alternating logic transitions with a relatively slow slew rate ...

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... Lattice Semiconductor Figure 2-40. SERDES/PCS Quads (LatticeECP3-150) Table 2-13. LatticeECP3 SERDES Standard Support Standard PCI Express 1.1 Gigabit Ethernet SGMII XAUI Serial RapidIO Type I, Serial RapidIO Type II, Serial RapidIO Type III CPRI-1, CPRI-2, CPRI-3, CPRI-4 SD-SDI (259M, 344M) HD-SDI (292M) 3G-SDI ...

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... Lattice Semiconductor Table 2-14. Available SERDES Quads per LatticeECP3 Devices Package ECP3-17 256 ftBGA 1 484 fpBGA 1 672 fpBGA — 1156 fpBGA — SERDES Block A SERDES receiver channel may receive the serial differential data stream, equalize the signal, perform Clock and Data Recovery (CDR) and de-serialize the data stream before passing the 8- or 10-bit data to the PCS logic. The SERDES transmitter channel may receive the parallel 8- or 10-bit data, serialize the data and transmit the serial bit stream through the differential drivers ...

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... Lattice Semiconductor The Diamond and ispLEVER design tools support all modes of the PCS. Most modes are dedicated to applications associated with a specific industry standard data protocol. Other more general purpose modes allow users to define their own operation. With these tools, the user can define the mode for each quad in a design. ...

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... Lattice Semiconductor reference clock will cause a violation of the Gigabit Ethernet, Serial RapidIO and SGMII transmit jitter specifica- tions. For further information on SERDES, please see TN1176, IEEE 1149.1-Compliant Boundary Scan Testability All LatticeECP3 devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant Test Access Port (TAP) ...

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... Lattice Semiconductor system FPGA. After the system is running with a basic configuration, a new boot image can be downloaded remotely and stored in a separate location in the configuration storage device. Any time after the update the LatticeECP3 can be re-booted from this new configuration file. If there is a problem, such as corrupt data dur- ing download or incorrect version number with this new boot image, the LatticeECP3 device can revert back to the original backup golden configuration and try again ...

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... Lattice Semiconductor Density Shifting The LatticeECP3 family is designed to ensure that different density devices in the same family and in the same package have the same pinout. Furthermore, the architecture ensures a high success rate when performing design migration from lower density devices to higher density devices. In many cases also possible to shift a lower uti- lization design targeted for a high-density device to a lower density device ...

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... LatticeECP3 SERDES/PCS Usage Guide © 2011 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...

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... Lattice Semiconductor Hot Socketing Specifications Symbol Parameter 4 IDK_HS Input or I/O Leakage Current 5 IDK Input or I/O Leakage Current and V should rise/fall monotonically. CC CCAUX CCIO additive LVCMOS and LVTTL only. 4. Applicable to general purpose I/O pins located on the top and bottom sides of the device. ...

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... Lattice Semiconductor DC Electrical Characteristics Symbol Parameter Input or I/O Low Leakage Input or I/O High Leakage IH I I/O Active Pull-up Current PU I I/O Active Pull-down Current PD I Bus Hold Low Sustaining Current V BHLS I Bus Hold High Sustaining Current V BHHS Bus Hold Low Overdrive Current 0  V ...

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... Lattice Semiconductor LatticeECP3 Supply Current (Standby) Over Recommended Operating Conditions Symbol I Core Power Supply Current CC I Auxiliary Power Supply Current CCAUX I PLL Power Supply Current (Per PLL) CCPLL I Bank Power Supply Current (Per Bank) CCIO I JTAG Power Supply Current CCJ I Transmit, Receive, PLL and Reference Clock Buffer Power Supply CCA 1 ...

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... Lattice Semiconductor SERDES Power Supply Requirements Symbol Standby (Power Down CCA-SB CCA I Input buffer current (per channel) CCIB-SB I Output buffer current (per channel) CCOB-SB Operating (Data Rate = 3.2 Gbps CCA-OP CCA I Input buffer current (per channel) CCIB-OP I Output buffer current (per channel) CCOB-OP Operating (Data Rate = 2 ...

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... Lattice Semiconductor sysI/O Recommended Operating Conditions Standard Min. 2 LVCMOS33 3.135 LVCMOS33D 3.135 2 LVCMOS25 2.375 LVCMOS18 1.71 LVCMOS15 1.425 2 LVCMOS12 1.14 2 LVTTL33 3.135 PCI33 3.135 3 SSTL15 1.43 2 SSTL18_I, II 1.71 2 SSTL25_I, II 2.375 2 SSTL33_I, II 3.135 2 HSTL15_I 1.425 2 HSTL18_I, II 1.71 2 LVDS25 2.375 LVDS25E 2.375 1 MLVDS 2 ...

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... Lattice Semiconductor sysI/O Single-Ended DC Electrical Characteristics V IL Input/Output Standard Min. (V) Max. (V) LVCMOS33 -0.3 0.8 LVCMOS25 -0.3 0.7 LVCMOS18 -0.3 0.35 V LVCMOS15 -0.3 0.35 V LVCMOS12 -0.3 0.35 V LVTTL33 -0.3 0.8 PCI33 -0.3 0.3 V SSTL18_I -0.3 V REF SSTL18_II -0.3 V REF (DDR2 Memory) SSTL2_I -0 ...

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... Lattice Semiconductor sysI/O Differential Electrical Characteristics LVDS25 Parameter Description Input Voltage INP INM 1 V Input Common Mode Voltage CM V Differential Input Threshold THD I Input Current IN V Output High Voltage for Output Low Voltage for Output Voltage Differential OD Change in V Between High and  ...

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... Lattice Semiconductor LVDS25E The top and bottom sides of LatticeECP3 devices support LVDS outputs via emulated complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The scheme shown in Figure 3-1 is one possible solution for point-to-point signals. Figure 3-1. LVDS25E Output Termination Example VCCIO = 2.5V (± ...

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... Lattice Semiconductor BLVDS25 The LatticeECP3 devices support the BLVDS standard. This standard is emulated using complementary LVCMOS outputs in conjunction with a parallel external resistor across the driver outputs. BLVDS is intended for use when multi-drop and bi-directional multi-point differential signaling is required. The scheme shown in Figure 3-2 is one possible solution for bi-directional multi-point differential signals ...

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... Lattice Semiconductor LVPECL33 The LatticeECP3 devices support the differential LVPECL standard. This standard is emulated using complemen- tary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The LVPECL input standard is supported by the LVDS differential input buffer. The scheme shown in Figure 3-3 is one possible solution for point-to-point signals ...

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... Lattice Semiconductor RSDS25E The LatticeECP3 devices support differential RSDS and RSDSE standards. This standard is emulated using com- plementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The RSDS input stan- dard is supported by the LVDS differential input buffer. The scheme shown in Figure 3-4 is one possible solution for RSDS standard implementation ...

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... Lattice Semiconductor MLVDS25 The LatticeECP3 devices support the differential MLVDS standard. This standard is emulated using complemen- tary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The MLVDS input standard is supported by the LVDS differential input buffer. The scheme shown in Figure 3-5 is one possible solution for MLVDS standard implementation ...

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... Lattice Semiconductor Typical Building Block Function Performance Pin-to-Pin Performance (LVCMOS25 12mA Drive) Basic Functions 16-bit Decoder 32-bit Decoder 64-bit Decoder 4:1 MUX 8:1 MUX 16:1 MUX 32:1 MUX 1. These functions were generated using the ispLEVER design tool. Exact performance may vary with device and tool version. The tool uses internal parameters that have been characterized but are not tested on every device ...

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... Lattice Semiconductor Register-to-Register Performance 18x18 Multiply/Accumulate (Input & Output Registers) 18x18 Multiply-Add/Sub (All Registers) 1. These timing numbers were generated using ispLEVER tool. Exact performance may vary with device and tool version. The tool uses inter- nal parameters that have been characterized but are not tested on every device. ...

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... Lattice Semiconductor LatticeECP3 External Switching Characteristics Over Recommended Commercial Operating Conditions Parameter Description Clocks Primary Clock 6 f Frequency for Primary Clock Tree MAX_PRI t Clock Pulse Width for Primary Clock ECP3-150EA W_PRI t Primary Clock Skew Within a Device ECP3-150EA SKEW_PRI t Primary Clock Skew Within a Bank ...

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... Lattice Semiconductor LatticeECP3 External Switching Characteristics (Continued) Over Recommended Commercial Operating Conditions Parameter Description Clock to Data Setup - PIO Input t SU_DEL Register with Data Input Delay Clock to Data Hold - PIO Input t H_DEL Register with Input Data Delay Clock Frequency of I/O and PFU ...

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... Lattice Semiconductor LatticeECP3 External Switching Characteristics (Continued) Over Recommended Commercial Operating Conditions Parameter Description Clock to Data Hold - PIO Input t HPLL Register Clock to Data Setup - PIO Input t SU_DELPLL Register with Data Input Delay Clock to Data Hold - PIO Input t H_DELPLL Register with Input Data Delay ...

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... Lattice Semiconductor LatticeECP3 External Switching Characteristics (Continued) Over Recommended Commercial Operating Conditions Parameter Description f DDRX1 Clock Frequency MAX_GDDR Generic DDRX1 Inputs with Clock and Data (>10 Bits Wide) Aligned at Pin (GDDRX1_RX.SCLK.Aligned) Using DLL - CLKIN Pin for Clock Input Data Left, Right and Top Sides and Clock Left and Right Sides ...

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... Lattice Semiconductor LatticeECP3 External Switching Characteristics (Continued) Over Recommended Commercial Operating Conditions Parameter Description f DDRX2 Clock Frequency MAX_GDDR t Data Setup Before CLK DVACLKGDDR t Data Hold After CLK DVECLKGDDR f DDRX2 Clock Frequency MAX_GDDR Top Side Using PCLK Pin for Clock Input t Data Setup Before CLK ...

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... Lattice Semiconductor LatticeECP3 External Switching Characteristics (Continued) Over Recommended Commercial Operating Conditions Parameter Description f DDRX2 Clock Frequency MAX_GDDR t Data Setup Before CLK DVACLKGDDR t Data Hold After CLK DVECLKGDDR f DDRX2 Clock Frequency MAX_GDDR Generic DDRX2 Inputs with Clock and Data (<10 Bits Wide) Centered at Pin (GDDRX2_RX.DQS.Centered) Using DQS ...

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... Lattice Semiconductor LatticeECP3 External Switching Characteristics (Continued) Over Recommended Commercial Operating Conditions Parameter Description Generic DDRX1 Output with Clock and Data (<10 Bits Wide) Centered at Pin (GDDRX1_TX.DQS.Centered) Left and Right Sides t Data Valid Before CLK DVBGDDR t Data Valid After CLK DVAGDDR ...

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... Lattice Semiconductor LatticeECP3 External Switching Characteristics (Continued) Over Recommended Commercial Operating Conditions Parameter Description t Data Valid After DQS DQVAS f DDR3 clock frequency MAX_DDR3 DDR3 Clock Timing 9 t (avg) Average High Pulse Width (avg) Average Low Pulse Width CL Output Clock Period Jitter During ...

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... Lattice Semiconductor Figure 3-6. Generic DDRX1/DDRX2 (With Clock and Data Edges Aligned) t DIBGDDR CLK Data (TDAT, TCTL) t DIAGDDR RDTCLK Data (RDAT, RCTL) t DVACLKGDDR t Figure 3-7. DDR/DDR2/DDR3 Parameters DQS DQ t DQVBS t DQVAS DQS DQ t DVADQ Transmit Parameters t DIAGDDR t DIBGDDR Receive Parameters t DVACLKGDDR ...

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... Lattice Semiconductor Figure 3-8. Generic DDRX1/DDRX2 (With Clock Center on Data Window) CLOCK DATA t DVBCKGDDR t DVACKGDDR CLOCK DATA t SUGDDR t HGDDR Transmit Parameters t DVACKGDDR t DVBCKGDDR Receive Parameters t SUGDDR t HGDDR 3-25 DC and Switching Characteristics LatticeECP3 Family Data Sheet ...

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... Lattice Semiconductor LatticeECP3 Internal Switching Characteristics Over Recommended Commercial Operating Conditions Parameter Description PFU/PFF Logic Mode Timing t LUT4 delay ( inputs to F output) LUT4_PFU t LUT6 delay ( inputs to OFX output) LUT6_PFU t Set/Reset to output of PFU (Asynchronous) LSR_PFU Asynchronous Set/Reset recovery time for t LSRREC_PFU PFU Logic ...

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... Lattice Semiconductor LatticeECP3 Internal Switching Characteristics Over Recommended Commercial Operating Conditions Parameter Description t Hold Write/Read Enable to EBR Memory HWREN_EBR Clock Enable Setup Time to EBR Output t SUCE_EBR Register Clock Enable Hold Time to EBR Output t HCE_EBR Register Byte Enable Set-Up Time to EBR Output ...

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... Lattice Semiconductor Timing Diagrams Figure 3-9. Read/Write Mode (Normal) CLKA CSA WEA ADA DIA D0 DOA Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive edge of the clock. Figure 3-10. Read/Write Mode with Input and Output Registers ...

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... Lattice Semiconductor Figure 3-11. Write Through (SP Read/Write on Port A, Input Registers Only) CLKA CSA WEA ADA DIA Data from Prev Read DOA or Write Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive edge of the clock. ...

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... Lattice Semiconductor LatticeECP3 Family Timing Adders Over Recommended Commercial Operating Conditions Buffer Type Input Adjusters LVDS25E LVDS, Emulated, VCCIO = 2.5V LVDS25 LVDS, VCCIO = 2.5V BLVDS25 BLVDS, Emulated, VCCIO = 2.5V MLVDS25 MLVDS, Emulated, VCCIO = 2.5V RSDS25 RSDS, VCCIO = 2.5V PPLVDS Point-to-Point LVDS ...

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... Lattice Semiconductor LatticeECP3 Family Timing Adders Over Recommended Commercial Operating Conditions Buffer Type RSDS25 RSDS, VCCIO = 2.5V PPLVDS Point-to-Point LVDS, Emulated, VCCIO = 2.5V LVPECL33 LVPECL, Emulated, VCCIO = 3.0V HSTL18_I HSTL_18 class I 8mA drive, VCCIO = 1.8V HSTL18_II HSTL_18 class II, VCCIO = 1.8V HSTL18D_I ...

Page 85

... Lattice Semiconductor LatticeECP3 Family Timing Adders Over Recommended Commercial Operating Conditions Buffer Type LVCMOS15_4mA LVCMOS 1.5 4mA drive, fast slew rate LVCMOS15_8mA LVCMOS 1.5 8mA drive, fast slew rate LVCMOS12_2mA LVCMOS 1.2 2mA drive, fast slew rate LVCMOS12_6mA LVCMOS 1.2 6mA drive, fast slew rate LVCMOS33_4mA LVCMOS 3 ...

Page 86

... Lattice Semiconductor LatticeECP3 Maximum I/O Buffer Speed Buffer Maximum Input Frequency LVDS25 MLVDS25 BLVDS25 PPLVDS TRLVDS Mini LVDS LVPECL33 HSTL18 (all supported classes) HSTL15 SSTL33 (all supported classes) SSTL25 (all supported classes) SSTL18 (all supported classes) LVTTL33 LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 ...

Page 87

... Lattice Semiconductor LatticeECP3 Maximum I/O Buffer Speed (Continued) Buffer PCI33 1. These maximum speeds are characterized but not tested on every device. 2. Maximum I/O speed for differential output standards emulated with resistors depends on the layout. 3. LVCMOS timing is measured with the load specified in the Switching Test Conditions table of this document. ...

Page 88

... Lattice Semiconductor sysCLOCK PLL Timing Parameter Descriptions Input clock frequency (CLKI CLKFB) Output clock frequency (CLKOP, f OUT CLKOS) f K-Divider output frequency OUT1 f K2-Divider output frequency OUT2 f PLL VCO frequency VCO 3 f Phase detector input frequency PFD AC Characteristics t Programmable delay unit PA Output clock duty cycle ...

Page 89

... Lattice Semiconductor DLL Timing Parameter Description Input reference clock frequency (on-chip or  f REF off-chip) f Feedback clock frequency (on-chip or off-chip Output clock frequency, CLKOP CLKOP 2 f Output clock frequency, CLKOS CLKOS t Output clock period jitter (clean input) PJIT Output clock duty cycle (at 50% levels, 50% duty ...

Page 90

... Lattice Semiconductor SERDES High-Speed Data Transmitter Table 3-6. Serial Output Timing and Levels Symbol Description V Differential swing (1.44V setting) TX-DIFF-P-P-1.44 V Differential swing (1.35V setting) TX-DIFF-P-P-1.35 V Differential swing (1.26V setting) TX-DIFF-P-P-1.26 V Differential swing (1.13V setting) TX-DIFF-P-P-1.13 V Differential swing (1.04V setting) TX-DIFF-P-P-1.04 V Differential swing (0.92V setting) TX-DIFF-P-P-0 ...

Page 91

... Lattice Semiconductor Table 3-7. Channel Output Jitter Description Frequency Deterministic 3.125 Gbps Random 3.125 Gbps Total 3.125 Gbps Deterministic 2.5Gbps Random 2.5Gbps Total 2.5Gbps Deterministic 1.25 Gbps Random 1.25 Gbps Total 1.25 Gbps Deterministic 622 Mbps Random 622 Mbps Total 622 Mbps ...

Page 92

... Lattice Semiconductor SERDES/PCS Block Latency Table 3-8 describes the latency of each functional block in the transmitter and receiver. Latency is given in parallel clock cycles. Figure 3-12 shows the location of each block. Table 3-8. SERDES/PCS Latency Breakdown Item Description 1 Transmit Data Latency FPGA Bridge - Gearing disabled with different clocks ...

Page 93

... Lattice Semiconductor SERDES High Speed Data Receiver Table 3-9. Serial Input Data Specifications Symbol Stream of nontransitions RX-CID S (CID = Consecutive Identical Digits Differential input sensitivity RX-DIFF-S V Input levels RX-IN V Input common mode range (DC coupled) RX-CM-DC V Input common mode range (AC coupled) RX-CM- SCDR re-lock time ...

Page 94

... Lattice Semiconductor Table 3-11. Periodic Receiver Jitter Tolerance Specification Description Frequency Periodic 2.97 Gbps Periodic 2.5 Gbps Periodic 1.485 Gbps Periodic 622 Mbps Periodic 150 Mbps Note: Values are measured with PRBS 2 quiet, voltages are nominal, room temperature. DC and Switching Characteristics ...

Page 95

... Lattice Semiconductor SERDES External Reference Clock The external reference clock selection and its interface are a critical part of system applications for this product. Table 3-12 specifies reference clock requirements, over the full range of operating conditions. Table 3-12. External Reference Clock Specification (refclkp/refclkn) ...

Page 96

... Lattice Semiconductor Figure 3-14. XAUI Jitter Transfer – 3.125 Gbps -10 -15 -20 0.01 Figure 3-15. CPRI E.24 Jitter Transfer – 2.5 Gbps -10 -15 -20 0.1 1 Frequency (MHz) REFCLK=312.5MHz REFCLK=156.25MHz REFCLK=125MHz 0.01 0.1 1 Frequency (MHz) REFCLK=250MHz REFCLK=156.26MHz REFCLK=125MHz REFCLK=100MHz 3-43 DC and Switching Characteristics LatticeECP3 Family Data Sheet ...

Page 97

... Lattice Semiconductor Figure 3-16. GbE Jitter Transfer – 1.25 Gbps -10 -15 -20 0.01 Figure 3-17. CPRI E6 Jitter Transfer – 622 Mbps -10 -15 -20 -25 -30 -35 -40 0.01 0.1 1 Frequency (MHz) REFCLK=125MHz REFCLK=62.5MHz 0.1 1 Frequency (MHz) REFCLK=62.5MHz 3-44 DC and Switching Characteristics LatticeECP3 Family Data Sheet ...

Page 98

... Lattice Semiconductor PCI Express Electrical and Timing Characteristics AC and DC Characteristics Symbol 1 Transmit UI Unit interval V Differential peak-to-peak output voltage TX-DIFF_P-P De-emphasis differential output voltage V TX-DE-RATIO ratio RMS AC peak common-mode output V TX-CM-AC_P voltage Amount of voltage change allowed dur- V TX-RCV-DETECT ing receiver detection common mode voltage ...

Page 99

... Lattice Semiconductor XAUI/Serial Rapid I/O Type 3/CPRI LV E.30 Electrical and Timing  Characteristics AC and DC Characteristics Table 3-13. Transmit Symbol Description T Differential rise/fall time RF Z Differential impedance TX_DIFF_DC Output data deterministic jitter TX_DDJ Total output data jitter TX_TJ 1. Total jitter includes both deterministic jitter and random jitter. ...

Page 100

... Lattice Semiconductor Figure 3-18. XAUI Sinusoidal Jitter Tolerance Mask Note: The sinusoidal jitter tolerance is measured with at least 0.37UIpp of Deterministic jitter (Dj) and the sum of Dj and Rj (random jitter least 0.55UIpp. Therefore, the sum of Dj, Rj and Sj (sinusoidal jitter least 0.65UIpp (Dj = 0.37 0.18 0.1). ...

Page 101

... Lattice Semiconductor Serial Rapid I/O Type 2/CPRI LV E.24 Electrical and Timing Characteristics AC and DC Characteristics Table 3-15. Transmit Symbol Description 1 T Differential rise/fall time RF Z Differential impedance TX_DIFF_DC Output data deterministic jitter TX_DDJ Total output data jitter TX_TJ 1. Rise and Fall times measured with board trace, connector and approximately 2.5pf load. ...

Page 102

... Lattice Semiconductor Gigabit Ethernet/Serial Rapid I/O Type 1/SGMII/CPRI LV E.12 Electrical and Timing Characteristics AC and DC Characteristics Table 3-17. Transmit Symbol T Differential rise/fall time RF Z Differential impedance TX_DIFF_DC Output data deterministic jitter TX_DDJ Total output data jitter TX_TJ 1. Rise and fall times measured with board trace, connector and approximately 2.5pf load. ...

Page 103

... Lattice Semiconductor SMPTE SD/HD-SDI/3G-SDI (Serial Digital Interface) Electrical and Timing Characteristics AC and DC Characteristics Table 3-19. Transmit Symbol Description BR Serial data rate SDO 2 T Serial output jitter, alignment JALIGNMENT 2 T Serial output jitter, alignment JALIGNMENT Serial output jitter, alignment JALIGNMENT T Serial output jitter, timing ...

Page 104

... Lattice Semiconductor HDMI (High-Definition Multimedia Interface) Electrical and Timing  Characteristics AC and DC Characteristics Table 3-22. Transmit and Receive Symbol Transmit Intra-pair Skew Inter-pair Skew TMDS Differential Clock Jitter Receive R Termination Resistance T V Input AC Common Mode Voltage (50-ohm Setting) ICM TMDS Clock Jitter Clock Jitter Tolerance 1 ...

Page 105

... Lattice Semiconductor Figure 3-19. Test Loads Test Loads V DDIO CMOS outputs including probe and jig capacitance, 3pF max open closed for closed open for Timing Jitter Bandpass 0db Slopes: 20dB/Decade Stopband Rejection <20dB 75Ω 1% SDO SDO Hi-Z test eqpt. ≥ 5Ωk ...

Page 106

... Lattice Semiconductor LatticeECP3 sysCONFIG Port Timing Specifications Parameter POR, Configuration Initialization, and Wakeup Time from the Application the Last to Cross the POR Trip Point) to the Rising Edge of ICFG INITN t Time from t to the Valid Master MCLK VMC ICFG t PROGRAMN Low Time to Start Configuration ...

Page 107

... Lattice Semiconductor LatticeECP3 sysCONFIG Port Timing Specifications (Continued) Parameter t HOLDN Low Hold Time (Relative to CCLK) CHHH Master and Slave SPI (Continued) t HOLDN High Hold Time (Relative to CCLK) CHHL t HOLDN High Setup Time (Relative to CCLK) HHCH t HOLDN to Output High-Z HLQZ t HOLDN to Output Low-Z HHQX 1 ...

Page 108

... Lattice Semiconductor Figure 3-21. sysCONFIG Parallel Port Write Cycle 1 CCLK CS1N CSN WRITEN BUSY D[0: Master Parallel Mode the FPGA provides CCLK (MCLK). In Slave Parallel Mode the external device provides CCLK. Figure 3-22. sysCONFIG Master Serial Port Timing CCLK (output) DIN DOUT Figure 3-23 ...

Page 109

... Lattice Semiconductor Figure 3-24. Power-On-Reset (POR) Timing CCAUX V 1 CCIO8 INITN DONE 2 CCLK 3 CFG[2:0] 1. Time taken from Device Master Mode (SPI, SPIm). 3. The CFG pins are normally static (hard wired). Figure 3-25. sysCONFIG Port Timing t ICFG t VMC VCC t PRGM t PRGMRJ CCLK ...

Page 110

... Lattice Semiconductor Figure 3-26. Configuration from PROGRAMN Timing PROGRAMN INITN DONE CCLK CFG[2:0] 1 USER I/O 1. The CFG pins are normally static (hard wired) Figure 3-27. Wake-Up Timing PROGRAMN INITN DONE CCLK USER I/O t PRGMRJ t DPPINIT t DINITD t IODISS Wake-Up t MWC t IOENSS 3-57 ...

Page 111

... Lattice Semiconductor Figure 3-28. Master SPI Configuration Waveforms Capture CR0 VCC PROGRAMN DONE INITN CSSPIN CCLK SISPI SOSPI DC and Switching Characteristics Capture CFGx … … Opcode Address 3-58 LatticeECP3 Family Data Sheet … 127 128 Ignore Valid Bitstream ...

Page 112

... Lattice Semiconductor JTAG Port Timing Specifications Symbol f TCK clock frequency MAX t TCK [BSCAN] clock pulse width BTCP t TCK [BSCAN] clock pulse width high BTCPH t TCK [BSCAN] clock pulse width low BTCPL t TCK [BSCAN] setup time BTS t TCK [BSCAN] hold time BTH ...

Page 113

... Lattice Semiconductor Switching Test Conditions Figure 3-30 shows the output test load that is used for AC testing. The specific values for resistance, capacitance, voltage, and other test conditions are shown in Table 3-23. Figure 3-30. Output Test Load, LVTTL and LVCMOS Standards Table 3-23. Test Fixture Required Components, Non-Terminated Interfaces Test Condition LVTTL and other LVCMOS settings (L -> ...

Page 114

... Lattice Semiconductor sysI/O Differential Electrical Characteristics Transition Reduced LVDS (TRLVDS DC Specification) Symbol Description V Driver supply voltage (+/- 5%) CCO V Input differential voltage ID V Input common mode voltage ICM V Termination supply voltage CCO R Termination resistance (off-chip) T Note: LatticeECP3 only supports the TRLVDS receiver. Transmitter ...

Page 115

... Lattice Semiconductor Point-to-Point LVDS (PPLVDS) Description Output driver supply (+/- 5%) Input differential voltage Input common mode voltage Output differential voltage Output common mode voltage RSDS Parameter Symbol V Output voltage, differential Output voltage, common mode OS I Differential driver output current RSDS V Input voltage differential ...

Page 116

... PCLK[T, C][n:0]_[3:0] © 2011 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com ...

Page 117

... Lattice Semiconductor Signal Descriptions (Cont.) Signal Name [LOC]DQS[num] [LOC]DQ[num] Test and Programming (Dedicated Pins) TMS TCK TDI TDO VCCJ Configuration Pads (Used During sysCONFIG) CFG[2:0] INITN PROGRAMN DONE CCLK MCLK BUSY/SISPI CSN/SN/OEN CS1N/HOLDN/RDY WRITEN DOUT/CSON/CSSPI1N D[0]/SPIFASTN D1 D2 D3/SI D4/SO D5 D6/SPID1 ...

Page 118

... Lattice Semiconductor Signal Descriptions (Cont.) Signal Name D7/SPID0 DI/CSSPI0N/CEN 3 Dedicated SERDES Signals PCS[Index]_HDINNm PCS[Index]_HDOUTNm PCS[Index]_REFCLKN PCS[Index]_HDINPm PCS[Index]_HDOUTPm PCS[Index]_REFCLKP PCS[Index]_VCCOBm PCS[Index]_VCCIBm 1. When placing switching I/Os around these critical pins that are designed to supply the device with the proper reference or supply voltage, care must be given. ...

Page 119

... Lattice Semiconductor PICs and DDR Data (DQ) Pins Associated with the DDR Strobe (DQS) Pin PICs Associated with DQS Strobe For Left and Right Edges of the Device P[Edge] [n-3] P[Edge] [n-2] P[Edge] [n-1] P[Edge] [n] P[Edge] [n+1] P[Edge] [n+2] For Top Edge of the Device ...

Page 120

... Lattice Semiconductor Pin Information Summary Pin Information Summary Pin Type Bank 0 Bank 1 Bank 2 General Purpose Bank 3 Inputs/Outputs per Bank Bank 6 Bank 7 Bank 8 Bank 0 Bank 1 Bank 2 General Purpose Inputs per Bank 3 Bank Bank 6 Bank 7 Bank 8 Bank 0 Bank 1 Bank 2 General Purpose Outputs per ...

Page 121

... Lattice Semiconductor Pin Information Summary (Cont.) Pin Information Summary Pin Type Bank 0 Bank 1 Bank 2 Emulated Differential I/O per Bank 3 Bank Bank 6 Bank 7 Bank 8 Bank 0 Bank 1 Bank 2 Highspeed Differential I/O per Bank 3 Bank Bank 6 Bank 7 Bank 8 Bank 0 Bank 1 Bank 2 Total Single Ended/ Total ...

Page 122

... Lattice Semiconductor Pin Information Summary (Cont.) Pin Information Summary Pin Type Bank 0 Bank 1 Bank 2 Emulated Differential  Bank 3 I/O per Bank Bank 6 Bank 7 Bank 8 Bank 0 Bank 1 Bank 2 High-Speed Differential I/ Bank 3 O per Bank Bank 6 Bank 7 Bank 8 Bank 0 Bank 1 Bank 2 Total Single-Ended/ Total Differential I/O ...

Page 123

... Lattice Semiconductor Pin Information Summary (Cont.) Pin Information Summary Pin Type Bank 0 Bank 1 Bank 2 General Purpose Bank 3 Inputs/Outputs per bank Bank 6 Bank 7 Bank 8 Bank 0 Bank 1 Bank 2 General Purpose Inputs per Bank 3 Bank Bank 6 Bank 7 Bank 8 Bank 0 Bank 1 Bank 2 General Purpose Outputs per ...

Page 124

... Lattice Semiconductor Pin Information Summary (Cont.) Pin Information Summary Pin Type Bank 0 Bank 1 Bank 2 Emulated Differential I/O  Bank 3 per Bank Bank 6 Bank 7 Bank 8 Bank 0 Bank 1 Bank 2 Highspeed Differential I/O  Bank 3 per Bank Bank 6 Bank 7 Bank 8 Bank 0 Bank 1 Bank 2 Total Single Ended/ ...

Page 125

... Lattice Semiconductor Logic Signal Connections Package pinout information can be found under “Data Sheets” on the LatticeECP3 product pages on the Lattice website at www.latticesemi.com/products/fpga/ecp3 pinout information from within ispLEVER Design Planner, select View > Package View. Then select Select File > Export and choose a type of output file. To create a pin information file from within Diamond select Tools > ...

Page 126

... Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com LatticeECP3 Family Data Sheet LFE3 – XXX XX – X XXXXXX X Commercial Industrial ECP3 ...

Page 127

... LFE3-35EA-8FTN256C 1.2V LFE3-35EA-6FN484C 1.2V LFE3-35EA-7FN484C 1.2V LFE3-35EA-8FN484C 1.2V LFE3-35EA-6FN672C 1.2V LFE3-35EA-7FN672C 1.2V LFE3-35EA-8FN672C 1.2V Part Number Voltage LFE3-70EA-6FN484C 1.2V LFE3-70EA-7FN484C 1.2V LFE3-70EA-8FN484C 1.2V LFE3-70EA-6FN672C 1.2V LFE3-70EA-7FN672C 1.2V LFE3-70EA-8FN672C 1.2V LFE3-70EA-6FN1156C 1.2V LFE3-70EA-7FN1156C 1.2V LFE3-70EA-8FN1156C 1.2V LatticeECP3 Family Data Sheet Commercial Grade ...

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... LFE3-150EA-7FN1156C 1.2V LFE3-150EA-8FN1156C 1.2V Part Number Voltage LFE3-150EA-6FN672CTW* LFE3-150EA-7FN672CTW* LFE3-150EA-8FN672CTW* LFE3-150EA-6FN1156CTW* LFE3-150EA-7FN1156CTW* LFE3-150EA-8FN1156CTW* *Note: Specifications for the LFE3-150EA-spFNpkgCTW and LFE3-150EA-spFNpkgITW devices, (where sp is the speed and pkg is the package), are the same as the LFE3-150EA-spFNpkgC and LFE3-150EA-spFNpkgI devices respectively, except as specified below. ...

Page 129

... LFE3-35EA-8FTN256I 1.2V LFE3-35EA-6FN484I 1.2V LFE3-35EA-7FN484I 1.2V LFE3-35EA-8FN484I 1.2V LFE3-35EA-6FN672I 1.2V LFE3-35EA-7FN672I 1.2V LFE3-35EA-8FN672I 1.2V Part Number Voltage LFE3-70EA-6FN484I 1.2V LFE3-70EA-7FN484I 1.2V LFE3-70EA-8FN484I 1.2V LFE3-70EA-6FN672I 1.2V LFE3-70EA-7FN672I 1.2V LFE3-70EA-8FN672I 1.2V LFE3-70EA-6FN1156I 1.2V LFE3-70EA-7FN1156I 1.2V LFE3-70EA-8FN1156I 1.2V LatticeECP3 Family Data Sheet Industrial Grade ...

Page 130

... LFE3-150EA-8FN1156ITW* *Note: Specifications for the LFE3-150EA-spFNpkgCTW and LFE3-150EA-spFNpkgITW devices, (where sp is the speed and pkg is the package), are the same as the LFE3-150EA-spFNpkgC and LFE3-150EA-spFNpkgI devices respectively, except as specified below. • The CTC (Clock Tolerance Circuit) inside the SERDES hard PCS in the TW device is not functional but it can be bypassed and implemented in soft IP. • ...

Page 131

... PCI: www.pcisig.com © 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...

Page 132

... DC and Switching Characteristics © 2011 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...

Page 133

... Lattice Semiconductor Date Version May 2009 01.1 DC and Switching (cont.) (cont.) Characteristics Pinout Information July 2009 01.2 Architecture DC and Switching Characterisitcs Pinout Information August 2009 01.3 DC and Switching Characterisitcs September 2009 01.4 Architecture DC and Switching Characterisitcs November 2009 01.5 Introduction Architecture ...

Page 134

... Updated Single-Ended DC table. Updated TRLVDS table and figure. Updated Serial Data Input Specifications table. Updated HDMI Transmit and Receive table. Added LFE3-150EA “TW” devices and footnotes to the Commercial and Industrial tables. Added Read-Before-Write information. Added footnote #6 to Maximum I/O Buffer Speed table. ...

Page 135

... Lattice Semiconductor Date Version December 2010 01.7EA Introduction (cont.) (cont.) Architecture DC and Switching Characteristics Pinout Information April 2011 01.8EA Architecture Section Corrected number of user I/Os Corrected the package type in Table 2-14 Available SERDES Quad per LatticeECP3 Devices. Updated description of General Purpose PLL Added additional information in the Flexible Quad SERDES Architecture section ...

Page 136

... Lattice Semiconductor Date Version April 2011 01.8EA DC and Switching (cont.) (cont.) Characteristics July 2011 01.9EA DC and Switching Characteristics Pinout Information Section Added data for 150 Mbps to SERDES Power Supply Requirements table. Updated Frequencies in Table 3-6 Serial Output Timing and Levels Added Data for 150 Mbps to Table 3-7 Channel Output Jitter ...