LFE3-70EA-8FN1156C

Manufacturer Part NumberLFE3-70EA-8FN1156C
Description66.5K LUTS, 490 I/O, SERDES, 1.2V, -8 SPEED, PB-FREE
ManufacturerLATTICE SEMICONDUCTOR
LFE3-70EA-8FN1156C datasheets

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Lattice Semiconductor
Table 2-5. DLL Signals
Signal
I/O
CLKI
I
Clock input from external pin or routing
CLKFB
I
DLL feed input from DLL output, clock net, routing or external pin
RSTN
I
Active low synchronous reset
ALUHOLD
I
Active high freezes the ALU
UDDCNTL
I
Synchronous enable signal (hold high for two cycles) from routing
CLKOP
O
The primary clock output
CLKOS
O
The secondary clock output with fine delay shift and/or division by 2 or by 4
LOCK
O
Active high phase lock indicator
INCI
I
Incremental indicator from another DLL via CIB.
GRAYI[5:0]
I
Gray-coded digital control bus from another DLL in time reference mode.
DIFF
O
Difference indicator when DCNTL is difference than the internal setting and update is needed.
INCO
O
Incremental indicator to other DLLs via CIB.
GRAYO[5:0]
O
Gray-coded digital control bus to other DLLs via CIB
LatticeECP3 devices have two general DLLs and four Slave Delay lines, two per DLL. The DLLs are in the lowest
EBR row and located adjacent to the EBR. Each DLL replaces one EBR block. One Slave Delay line is placed adja-
cent to the DLL and the duplicate Slave Delay line (in Figure 2-6) for the DLL is placed in the I/O ring between
Banks 6 and 7 and Banks 2 and 3.
The outputs from the DLL and Slave Delay lines are fed to the clock distribution network.
For more information, please see TN1178,
Figure 2-6. Top-Level Block Diagram, High-Speed DLL and Slave Delay Line
HOLD
GRAY_IN[5:0]
INC_IN
RSTN
GSRN
UDDCNTL
DCPS[5:0]
TPIO0 (L) OR TPIO1 (R)
GPLL_PIO
CIB (DATA)
CIB (CLK)
GDLL_PIO
Top ECLK1 (L) OR Top ECLK2 (R)
FB CIB (CLK)
Internal from CLKOP
GDLLFB_PIO
ECLK1
LatticeECP3 Family Data Sheet
Description
LatticeECP3 sysCLOCK PLL/DLL Design and Usage
4
LatticeECP3
3
High-Speed DLL
CLKI
2
1
0
4
3
CLKFB
2
1
0
DCNTL[5:0]
4
3
CLKI
2
Slave Delay Line
1
0
* This signal is not user accessible. It can only be used to feed the slave delay line.
2-9
Architecture
Guide.
CLKOP
CLKOS
LOCK
GRAY_OUT[5:0]
INC_OUT
DIFF
DCNTL[5:0]*
CLKO (to edge clock
muxes as CLKINDEL)

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