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- Integrated Circuits (ICs)/
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LFE3-70EA-8FN1156C
LFE3-70EA-8FN1156C | |
|---|---|
| Manufacturer Part Number | LFE3-70EA-8FN1156C |
| Description | 66.5K LUTS, 490 I/O, SERDES, 1.2V, -8 SPEED, PB-FREE |
| Manufacturer | LATTICE SEMICONDUCTOR |
| LFE3-70EA-8FN1156C datasheets |
|
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PrevNext
July 2011
Date
Version
February 2009
01.0
May 2009
01.1
Introduction
Architecture
DC and Switching
Characteristics
© 2011 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
LatticeECP3 Family Data Sheet
Section
—
Initial release.
All
Removed references to Parallel burst mode Flash.
Features - Changed 250 Mbps to 230 Mbps in Embedded SERDES bul-
leted section and added a footnote to indicate 230 Mbps applies to
8b10b and 10b12b applications.
Updated data for ECP3-17 in LatticeECP3 Family Selection Guide table.
Changed embedded memory from 552 to 700 Kbits in LatticeECP3
Family Selection Guide table.
Updated description for CLKFB in General Purpose PLL Diagram.
Corrected Primary Clock Sources text section.
Corrected Secondary Clock/Control Sources text section.
Corrected Secondary Clock Regions table.
Corrected note below Detailed sysDSP Slice Diagram.
Corrected Clock, Clock Enable, and Reset Resources text section.
Corrected ECP3-17 EBR number in Embedded SRAM in the
LatticeECP3 Family table.
Added On-Chip Termination Options for Input Modes table.
Updated Available SERDES Quads per LatticeECP3 Devices table.
Updated Simplified Channel Block Diagram for SERDES/PCS Block
diagram.
Updated Device Configuration text section.
Corrected software default value of MCCLK to be 2.5 MHz.
Updated VCCOB Min/Max data in Recommended Operating Conditions
table.
Corrected footnote 2 in sysIO Recommended Operating Conditions
table.
Added added footnote 7 for t
teristics table.
Added 2-to-1 Gearing text section and table.
Updated External Reference Clock Specification (refclkp/refclkn) table.
LatticeECP3 sysCONFIG Port Timing Specifications - updated t
information.
Added sysCONFIG Port Timing waveform.
Serial Input Data Specifications table, delete Typ data for V
Added footnote 4 to sysCLOCK PLL Timing table for t
Added SERDES/PCS Block Latency Breakdown table.
External Reference Clock Specifications table, added footnote 4, add
symbol name vREF-IN-DIFF.
Added SERDES External Reference Clock Waveforms.
Updated Serial Output Timing and Levels table.
Pin-to-pin performance table, changed "typically 3% slower" to "typically
slower".
7-1
Revision History
Data Sheet DS1021
Change Summary
to External Switching Charac-
SKEW_PRIB
RX-DIFF-S
.
PFD
DS1021 Revision History
DINIT
.
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