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LFE3-70EA-8FN1156C
LFE3-70EA-8FN1156C | |
|---|---|
| Manufacturer Part Number | LFE3-70EA-8FN1156C |
| Description | 66.5K LUTS, 490 I/O, SERDES, 1.2V, -8 SPEED, PB-FREE |
| Manufacturer | LATTICE SEMICONDUCTOR |
| LFE3-70EA-8FN1156C datasheets |
|
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PrevNext
Lattice Semiconductor
MAC DSP Element
In this case, the two operands, AA and AB, are multiplied and the result is added with the previous accumulated
value. This accumulated value is available at the output. The user can enable the input and pipeline registers, but
the output register is always enabled. The output register is used to store the accumulated value. The ALU is con-
figured as the accumulator in the sysDSP slice in the LatticeECP3 family can be initialized dynamically. A regis-
tered overflow signal is also available. The overflow conditions are provided later in this document. Figure 2-27
shows the MAC sysDSP element.
Figure 2-27. MAC DSP Element
C
SRIB
SRIA
I
Previous
DSP Slice
C_ALU
CIN
A_ALU
Rounding
0
IR = Input Register
PR = Pipeline Register
OR = Output Register
FR = Flag Register
From FPGA Core
AA
AB
OPCODE
IR
IR
MULTA
IR
PR
PR
A_ALU
0
AMUX
R= A ± B ± C
R = Logic (B, C)
OR
OR
To FPGA Core
2-25
Architecture
LatticeECP3 Family Data Sheet
BA
BB
SROB
IR
IR
IR
SROA
MULTB
PR
B_ALU
0
Next
DSP Slice
BMUX
COUT
ALU
=
=
FR
OR
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