LFE3-70EA-8FN1156C

Manufacturer Part NumberLFE3-70EA-8FN1156C
Description66.5K LUTS, 490 I/O, SERDES, 1.2V, -8 SPEED, PB-FREE
ManufacturerLATTICE SEMICONDUCTOR
LFE3-70EA-8FN1156C datasheets

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Lattice Semiconductor
MULTADDSUB DSP Element
In this case, the operands AA and AB are multiplied and the result is added/subtracted with the result of the multi-
plier operation of operands BA and BB. The user can enable the input, output and pipeline registers. Figure 2-29
shows the MULTADDSUB sysDSP element.
Figure 2-29. MULTADDSUB
C
SRIB
SRIA
IR
Previous
DSP Slice
C_ALU
CIN
A_ALU
Rounding
0
IR = Input Register
PR = Pipeline Register
OR = Output Register
FR = Flag Register
From FPGA Core
AA
AB
OPCODE
IR
IR
MULTA
IR
PR
PR
A_ALU
0
AMUX
R= A ± B ± C
R = Logic (B, C)
OR
OR
To FPGA Core
2-27
Architecture
LatticeECP3 Family Data Sheet
BA
BB
SROB
IR
IR
IR
SROA
MULTB
PR
B_ALU
0
Next
DSP Slice
BMUX
COUT
ALU
=
=
FR
OR