LFE3-70EA-8FN1156C

Manufacturer Part NumberLFE3-70EA-8FN1156C
Description66.5K LUTS, 490 I/O, SERDES, 1.2V, -8 SPEED, PB-FREE
ManufacturerLATTICE SEMICONDUCTOR
LFE3-70EA-8FN1156C datasheets

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Lattice Semiconductor
ALU Flags
The sysDSP slice provides a number of flags from the ALU including:
• Equal to zero (EQZ)
• Equal to zero with mask (EQZM)
• Equal to one with mask (EQOM)
• Equal to pattern with mask (EQPAT)
• Equal to bit inverted pattern with mask (EQPATB)
• Accumulator Overflow (OVER)
• Accumulator Underflow (UNDER)
• Either over or under flow supporting LatticeECP2 legacy designs (OVERUNDER)
Clock, Clock Enable and Reset Resources
Global Clock, Clock Enable and Reset signals from routing are available to every sysDSP slice. From four clock
sources (CLK0, CLK1, CLK2, and CLK3) one clock is selected for each input register, pipeline register and output
register. Similarly Clock Enable (CE) and Reset (RST) are selected at each input register, pipeline register and out-
put register.
Resources Available in the LatticeECP3 Family
Table 2-9 shows the maximum number of multipliers for each member of the LatticeECP3 family. Table 2-10 shows
the maximum available EBR RAM Blocks in each LatticeECP3 device. EBR blocks, together with Distributed RAM
can be used to store variables locally for fast DSP operations.
Table 2-9. Maximum Number of DSP Slices in the LatticeECP3 Family
Device
DSP Slices
ECP3-17
ECP3-35
ECP3-70
ECP3-95
ECP3-150
160
Table 2-10. Embedded SRAM in the LatticeECP3 Family
Device
ECP3-17
ECP3-35
ECP3-70
ECP3-95
ECP3-150
9x9 Multiplier
12
48
32
128
64
256
64
256
640
EBR SRAM Block
38
72
240
240
372
2-30
Architecture
LatticeECP3 Family Data Sheet
18x18 Multiplier
36x36 Multiplier
24
6
64
16
128
32
128
32
320
80
Total EBR SRAM
(Kbits)
700
1327
4420
4420
6850

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