LFE3-70EA-8FN1156C

Manufacturer Part NumberLFE3-70EA-8FN1156C
Description66.5K LUTS, 490 I/O, SERDES, 1.2V, -8 SPEED, PB-FREE
ManufacturerLATTICE SEMICONDUCTOR
LFE3-70EA-8FN1156C datasheets

Availability: By request

International delivery:

Warranty: 60 days

Shipping & payment terms

Added to cart

Select quantity

 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Page 31
32
Page 32
33
Page 33
34
Page 34
35
Page 35
36
Page 36
37
Page 37
38
Page 38
39
Page 39
40
Page 40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
Page 35/136

Download datasheet (3Mb)Embed
PrevNext
Lattice Semiconductor
Two adjacent PIOs can be joined to provide a differential I/O pair (labeled as “T” and “C”) as shown in Figure 2-32.
The PAD Labels “T” and “C” distinguish the two PIOs. Approximately 50% of the PIO pairs on the left and right
edges of the device can be configured as true LVDS outputs. All I/O pairs can operate as LVDS inputs.
Table 2-11. PIO Signal List
Name
Type
INDD
Input Data
IPA, INA, IPB, INB
Input Data
1
OPOSA, ONEGA
,
Output Data
1
OPOSB, ONEGB
CE
PIO Control
SCLK
PIO Control
LSR
PIO Control
ECLK1, ECLK2
PIO Control
1
ECLKDQSR
Read Control
1
DDRCLKPOL
Read Control
1
DDRLAT
Read Control
DEL[3:0]
Read Control
INCK
To Clock Distribution
and PLL
TS
Tristate Data
1
1
DQCLK0
, DQCLK1
Write Control
2
DQSW
Write Control
DYNDEL[7:0]
Write Control
DCNTL[6:0]
PIO Control
1
DATAVALID
Output Data
READ
For DQS_Strobe
DQSI
For DQS_Strobe
PRMBDET
For DQS_Strobe
GSRN
Control from routing Global Set/Reset
1. Signals available on left/right/top edges only.
2. Selected PIO.
PIO
The PIO contains four blocks: an input register block, output register block, tristate register block and a control logic
block. These blocks contain registers for operating in a variety of modes along with the necessary clock and selec-
tion logic.
Input Register Block
The input register blocks for the PIOs, in the left, right and top edges, contain delay elements and registers that can
be used to condition high-speed interface signals, such as DDR memory interfaces and source synchronous inter-
faces, before they are passed to the device core. Figure 2-33 shows the input register block for the left, right and
top edges. The input register block for the bottom edge contains one element to register the input signal and no
DDR registers. The following description applies to the input register block for PIOs in the left, right and top edges
only.
Description
Register bypassed input. This is not the same port as INCK.
Ports to core for input data
Output signals from core. An exception is the ONEGB port, used for tristate logic
at the DQS pad.
Clock enables for input and output block flip-flops.
System Clock (PCLK) for input and output/TS blocks. Connected from clock ISB.
Local Set/Reset
Edge clock sources. Entire PIO selects one of two sources using mux.
From DQS_STROBE, shifted strobe for memory interfaces only.
Ensures transfer from DQS domain to SCLK domain.
Used to guarantee INDDRX2 gearing by selectively enabling a D-Flip-Flop in dat-
apath.
Dynamic input delay control bits.
PIO treated as clock PIO, path to distribute to primary clocks and PLL.
Tristate signal from core (SDR)
Two clocks edges, 90 degrees out of phase, used in output gearing.
Used for output and tristate logic at DQS only.
Shifting of write clocks for specific DQS group, using 6:0 each step is approxi-
mately 25ps, 128 steps. Bit 7 is an invert (timing depends on input frequency).
There is also a static control for this 8-bit setting, enabled with a memory cell.
Original delay code from DDR DLL
Status flag from DATAVALID logic, used to indicate when input data is captured in
IOLOGIC and valid to core.
Read signal for DDR memory interface
Unshifted DQS strobe from input pad
DQSI biased to go high when DQSI is tristate, goes to input logic block as well as
core logic.
2-32
Architecture
LatticeECP3 Family Data Sheet

Related parts for LFE3-70EA-8FN1156C

Part Number DescriptionManufacturer Datasheet
  LFE3-70EA-6FN1156C 66.5K LUTS, 490 I/O, SERDES, 1.2V, -6 SPEED, PB-FREE LATTICE SEMICONDUCTOR
  LFE3-70E-7FN672C FPGA LatticeECP3™ Family 67000 Cells 65nm Technology 1.2V 672-Pin FBGA LATTICE SEMICONDUCTOR
  LFE3-70EA-7FN484C IC FPGA 66.5KLUTS 295I/O 484BGA Lattice
  LFE3-70EA-6FN484I IC FPGA 66.5KLUTS 295I/O 484BGA Lattice
  LFE3-70EA-7FN672C IC FPGA 66.5KLUTS 380I/O 672BGA Lattice
  LFE3-70EA-6FN672I IC FPGA 66.5KLUTS 380I/O 672BGA Lattice
  LFE3-70EA-7FN1156C IC FPGA 66.5KLUTS 490I/O 1156BGA Lattice
  LFE3-70EA-6FN1156I IC FPGA 66.5KLUTS 490I/O 1156BGA Lattice
  LFE3-70EA-6FN484C IC FPGA 67KLUTS 295I/O 484-BGA Lattice
  LFE3-70EA-7FN484I IC FPGA 67KLUTS 295I/O 484-BGA Lattice
  LFE3-70EA-7FN672I IC FPGA 67KLUTS 380I/O 672-BGA Lattice
  LFE3-70EA-8FN672C IC FPGA 67KLUTS 380I/O 672-BGA Lattice
  LFE3-70EA-7FN1156I IC FPGA 67KLUTS 490I/O 1156-BGA Lattice
  LFE3-70EA-8FN1156I IC FPGA 67KLUTS 490I/O 1156-BGA Lattice
  LFE3-70EA-8FN484I IC FPGA 66.5KLUTS 484FPBGA Lattice