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LFE3-70EA-8FN1156C
LFE3-70EA-8FN1156C | |
|---|---|
| Manufacturer Part Number | LFE3-70EA-8FN1156C |
| Description | 66.5K LUTS, 490 I/O, SERDES, 1.2V, -8 SPEED, PB-FREE |
| Manufacturer | LATTICE SEMICONDUCTOR |
| LFE3-70EA-8FN1156C datasheets |
|
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PrevNext
July 2011
Absolute Maximum Ratings
Supply Voltage V
. . . . . . . . . . . . . . . . . . . -0.5 to 1.32V
CC
Supply Voltage V
. . . . . . . . . . . . . . . . -0.5 to 3.75V
CCAUX
Supply Voltage V
. . . . . . . . . . . . . . . . . . -0.5 to 3.75V
CCJ
Output Supply Voltage V
. . . . . . . . . . . -0.5 to 3.75V
CCIO
Input or I/O Tristate Voltage Applied
Storage Temperature (Ambient) . . . . . . . . . -65 to 150°C
Junction Temperature (T
) . . . . . . . . . . . . . . . . . . +125°C
J
1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
2. Compliance with the Lattice
Thermal Management
3. All voltages referenced to GND.
4. Overshoot and undershoot of -2V to (V
Recommended Operating Conditions
Symbol
2
V
Core Supply Voltage
CC
Auxiliary Supply Voltage, Terminating Resistor Switching Power
2, 4
V
CCAUX
Supply (SERDES)
V
PLL Supply Voltage
CCPLL
2, 3
V
I/O Driver Supply Voltage
CCIO
2
V
Supply Voltage for IEEE 1149.1 Test Access Port
CCJ
V
and V
Input Reference Voltage
REF1
REF2
5
V
Termination Voltage
TT
t
Junction Temperature, Commercial Operation
JCOM
t
Junction Temperature, Industrial Operation
JIND
6
SERDES External Power Supply
Input Buffer Power Supply (1.2V)
V
CCIB
Input Buffer Power Supply (1.5V)
Output Buffer Power Supply (1.2V)
V
CCOB
Output Buffer Power Supply (1.5V)
V
Transmit, Receive, PLL and Reference Clock Buffer Power Supply
CCA
1. For correct operation, all supplies except V
usage.
2. If V
or V
is set to 1.2V, they must be connected to the same power supply as V
CCIO
CCJ
nected to the same power supply as V
3. See recommended voltages by I/O standard in subsequent table.
4. V
ramp rate must not exceed 30mV/µs during power-up when transitioning between 0V and 3.3V.
CCAUX
5. If not used, V
should be left floating.
TT
6. See TN1176,
LatticeECP3 SERDES/PCS Usage Guide
© 2011 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
LatticeECP3 Family Data Sheet
DC and Switching Characteristics
1, 2, 3
4
. . . . . . -0.5 to 3.75V
document is required.
+ 2) volts is permitted for a duration of <20ns.
IHMAX
1
Parameter
and V
must be held in their valid operation range. This is true independent of feature
REF
TT
.
CCAUX
for information on board considerations for SERDES power supplies.
3-1
Data Sheet DS1021
Min.
Max.
1.14
1.26
3.135
3.465
3.135
3.465
1.14
3.465
1.14
3.465
0.5
1.7
0.5
1.3125
0
85
-40
100
1.14
1.26
1.425
1.575
1.14
1.26
1.425
1.575
1.14
1.26
If V
or V
is set to 3.3V, they must be con-
CC.
CCIO
CCJ
DS1021
DC and Switching_02.0
Units
V
V
V
V
V
V
V
°C
°C
V
V
V
V
V
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