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LFE3-70EA-8FN1156C
LFE3-70EA-8FN1156C | |
|---|---|
| Manufacturer Part Number | LFE3-70EA-8FN1156C |
| Description | 66.5K LUTS, 490 I/O, SERDES, 1.2V, -8 SPEED, PB-FREE |
| Manufacturer | LATTICE SEMICONDUCTOR |
| LFE3-70EA-8FN1156C datasheets |
|
Availability: By request
International delivery:
Warranty: 60 days
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PrevNext
Lattice Semiconductor
LatticeECP3 External Switching Characteristics (Continued)
Over Recommended Commercial Operating Conditions
Parameter
Description
f
DDRX1 Clock Frequency
MAX_GDDR
Generic DDRX1 Inputs with Clock and Data (>10 Bits Wide) Aligned at Pin (GDDRX1_RX.SCLK.Aligned) Using DLL -
CLKIN Pin for Clock Input
Data Left, Right and Top Sides and Clock Left and Right Sides
t
Data Setup Before CLK
DVACLKGDDR
t
Data Hold After CLK
DVECLKGDDR
f
DDRX1 Clock Frequency
MAX_GDDR
Generic DDRX1 Inputs with Clock and Data (<10 Bits Wide) Centered at Pin (GDDRX1_RX.DQS.Centered) Using DQS
Pin for Clock Input
t
Data Setup After CLK
SUGDDR
t
Data Hold After CLK
HOGDDR
f
DDRX1 Clock Frequency
MAX_GDDR
Generic DDRX1 Inputs with Clock and Data (<10bits wide) Aligned at Pin (GDDRX1_RX.DQS.Aligned) Using DQS Pin
for Clock Input
Data and Clock Left and Right Sides
t
Data Setup Before CLK
DVACLKGDDR
t
Data Hold After CLK
DVECLKGDDR
f
DDRX1 Clock Frequency
MAX_GDDR
Generic DDRX2 Inputs with Clock and Data (>10 Bits Wide) Centered at Pin (GDDRX2_RX.ECLK.Centered) Using
PCLK Pin for Clock Input
Left and Right Sides
t
Data Setup Before CLK
SUGDDR
t
Data Hold After CLK
HOGDDR
f
DDRX2 Clock Frequency
MAX_GDDR
t
Data Setup Before CLK
SUGDDR
t
Data Hold After CLK
HOGDDR
f
DDRX2 Clock Frequency
MAX_GDDR
t
Data Setup Before CLK
SUGDDR
t
Data Hold After CLK
HOGDDR
f
DDRX2 Clock Frequency
MAX_GDDR
t
Data Setup Before CLK
SUGDDR
t
Data Hold After CLK
HOGDDR
f
DDRX2 Clock Frequency
MAX_GDDR
Generic DDRX2 Inputs with Clock and Data (>10 Bits Wide) Aligned at Pin (GDDRX2_RX.ECLK.Aligned)
Left and Right Side Using DLLCLKIN Pin for Clock Input
t
Data Setup Before CLK
DVACLKGDDR
t
Data Hold After CLK
DVECLKGDDR
f
DDRX2 Clock Frequency
MAX_GDDR
t
Data Setup Before CLK
DVACLKGDDR
t
Data Hold After CLK
DVECLKGDDR
f
DDRX2 Clock Frequency
MAX_GDDR
t
Data Setup Before CLK
DVACLKGDDR
t
Data Hold After CLK
DVECLKGDDR
DC and Switching Characteristics
LatticeECP3 Family Data Sheet
-8
Device
Min. Max. Min. Max. Min. Max.
All ECP3EA Devices
—
250
All ECP3EA Devices
—
0.225
All ECP3EA Devices 0.775
—
0.775
All ECP3EA Devices
—
250
All ECP3EA Devices 535
—
All ECP3EA Devices 535
—
All ECP3EA Devices
—
250
All ECP3EA Devices
—
0.225
All ECP3EA Devices 0.775
—
0.775
All ECP3EA Devices
—
250
ECP3-150EA
321
—
ECP3-150EA
321
—
ECP3-150EA
—
405
ECP3-70EA/95EA
321
—
ECP3-70EA/95EA
321
—
ECP3-70EA/95EA
—
405
ECP3-35EA
335
—
ECP3-35EA
335
—
ECP3-35EA
—
405
ECP3-17EA
335
—
ECP3-17EA
335
—
ECP3-17EA
—
405
ECP3-150EA
—
0.225
ECP3-150EA
0.775
—
0.775
ECP3-150EA
—
460
ECP3-70EA/95EA
—
0.225
ECP3-70EA/95EA
0.775
—
0.775
ECP3-70EA/95EA
—
460
ECP3-35EA
—
0.210
ECP3-35EA
0.790
—
0.790
3-19
1, 2
-7
-6
Units
—
250
—
250
MHz
—
0.225
—
0.225
UI
—
0.775
—
UI
—
250
—
250
MHz
535
—
535
—
ps
535
—
535
—
ps
—
250
—
250
MHz
—
0.225
—
0.225
UI
—
0.775
—
UI
—
250
—
250
MHz
403
—
471
—
ps
403
—
471
—
ps
—
325
—
280
MHz
403
—
535
—
ps
403
—
535
—
ps
—
325
—
250
MHz
425
—
535
—
ps
425
—
535
—
ps
—
325
—
250
MHz
425
—
535
—
ps
425
—
535
—
ps
—
325
—
250
MHz
—
0.225
—
0.225
UI
—
0.775
—
UI
—
385
—
345
MHz
—
0.225
—
0.225
UI
—
0.775
—
UI
—
385
—
311
MHz
—
0.210
—
0.210
UI
—
0.790
—
UI
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LFE3-70EA-7FN484I |
IC FPGA 67KLUTS 295I/O 484-BGA | Lattice |
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LFE3-70EA-7FN672I |
IC FPGA 67KLUTS 380I/O 672-BGA | Lattice |
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LFE3-70EA-8FN672C |
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LFE3-70EA-7FN1156I |
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LFE3-70EA-8FN1156I |
IC FPGA 67KLUTS 490I/O 1156-BGA | Lattice |
|
|
LFE3-70EA-8FN484I |
IC FPGA 66.5KLUTS 484FPBGA | Lattice | |
