AD7495BRZ Analog Devices Inc, AD7495BRZ Datasheet - Page 21

• Manufacturer Part Number: AD7495BRZ
• Description: ADC Single SAR 1MSPS 12-Bit Serial 8-Pin SOIC N
• Manufacturer: Analog Devices Inc

Specifications of AD7495BRZ

• Package: 8SOIC N
• Resolution: 12 Bit
• Sampling Rate: 1000 KSPS
• Architecture: SAR
• Number Of Analog Inputs: 1
• Digital Interface Type: Serial (SPI, QSPI, Microwire)
• Input Type: Voltage
• Signal To Noise Ratio: 68 dB
• Polarity Of Input Voltage: Unipolar
• Number Of Bits: 12
• Sampling Rate (per Second): 1M
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 10.5mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MICROPROCESSOR INTERFACING
The serial interface on the AD7475/AD7495 allows the parts
to be directly connected to a range of many different micro-
processors. This section explains how to interface the AD7475/
AD7495 with some of the more common microcontroller and
DSP serial interface protocols.
AD7475/AD7495 TO TMS320C5
The serial interface on the TMS320C5x/C54x uses a continuous
serial clock and frame synchronization signals to synchronize
the data transfer operations with peripheral devices like the
AD7475/AD7495. The CS input allows easy interfacing
between the TMS320C5x/C54x and the AD7475/AD7495
without any glue logic required. The serial port of the
TMS320C5x/C54x is set up to operate in burst mode with
internal CLKX (Tx serial clock) and FSX (Tx frame sync).
The serial port control register (SPC) must have the following
setup: FO = 0, FSM = 1, MCM = 1, and TXM = 1. The format
bit, FO, may be set to 1 to set the word length to 8 bits, in order
to implement the power-down modes on the AD7475/AD7495.
The connection diagram is shown in Figure 28. Note that for
signal processing applications, it is imperative that the frame
synchronization signal from the TMS320C5x/C54x provide
equidistant sampling. The V
takes the same supply voltage as that of the TMS320C5x/C54x.
This allows the ADC to operate at a higher voltage than the
serial interface, that is, TMS320C5x/C54x, if necessary.
*
ADDITIONAL PINS OMITTED FOR CLARITY
AD7475/AD7495*
SDATA
V
SCLK
DRIVE
Figure 28. Interfacing to the TMS320C5x/54x
CS
DRIVE
pin of the AD7475/AD7495
X
/C54
CLKX
CLKR
DR
FBX
FSR
TMS320C5x/C54x*
V
X
DD
Rev. B | Page 21 of 24
AD7475/AD7495 TO ADSP-21
The ADSP-21xx family of DSPs is interfaced directly to the
AD7475/AD7495 without any glue logic required. The V
pin of the AD7475/AD7495 takes the same supply voltage as
that of the ADSP-21xx. This allows the ADC to operate at a
higher voltage than the serial interface, that is, ADSP-21xx, if
necessary.
The SPORT control register should be set up as shown in Table 6.
Table 6.
SPORT Control Register Bits
TFSW = RFSW = 1
INVRFS = INVTFS = 1
DTYPE = 00
SLEN = 1111
ISCLK = 1
TFSR = RFSR = 1
IRFS = 0
ITFS = 1
To implement the power-down modes, SLEN should be set to
1001 to issue an 8-bit SCLK burst.
The connection diagram is shown in Figure 29. The ADSP-21xx
has the TFS and RFS of the SPORT tied together, with TFS set
as an output and RFS set as an input. The DSP operates in
alternate framing mode and the SPORT control register is set
up as described. The frame synchronization signal generated
on the TFS is tied to CS and, as with all signal processing
applications, equidistant sampling is necessary. However, in this
example, the timer interrupt is used to control the sampling rate
of the ADC and, under certain conditions, equidistant sampling
may not be achieved.
AD7475/AD7495*
*
ADDITIONAL PINS OMITTED FOR CLARITY
SDATA
V
SCLK
DRIVE
CS
Figure 29. Interfacing to the ADSP-21xx
Function
Alternate framing
Active low frame signal
Right-justify data
16-bit data words
Internal serial clock
Frame every word
XX
AD7475/AD7495
SCLK
DR
RFS
TFS
ADSP-21xx*
V
DD
DRIVE