RF Wireless Misc Switchable Rx-IC f/Industrial(433MHz)

ATA8202-PXQW

Manufacturer Part NumberATA8202-PXQW
DescriptionRF Wireless Misc Switchable Rx-IC f/Industrial(433MHz)
ManufacturerAtmel
ATA8202-PXQW datasheet
 

Specifications of ATA8202-PXQW

Package / CaseQFN-24Mounting StyleSMD/SMT
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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Features
Transparent RF Receiver ICs for 315 MHz (ATA8201) and 433.92 MHz (ATA8202) With
High Receiving Sensitivity
Fully Integrated PLL With Low Phase Noise VCO, PLL, and Loop Filter
High FSK/ASK Sensitivity:–105 dBm (ATA8201, FSK, 9.6 Kbits/s, Manchester, BER 10
–114 dBm (ATA8201, ASK, 2.4 Kbits/s, Manchester, BER 10
–104 dBm (ATA8202, FSK, 9.6 Kbits/s, Manchester, BER 10
–113 dBm (ATA8202, ASK, 2.4 Kbits/s, Manchester, BER 10
Supply Current: 6.5 mA in Active Mode (3V, 25°C, ASK Mode)
Data Rate: 1 Kbit/s to 10 Kbits/s Manchester ASK, 1 Kbit/s to 20 Kbits/s Manchester
FSK With Four Programmable Bit Rate Ranges
Switching Between Modulation Types ASK/FSK and Different Data Rates Possible in
1 ms Typically, Without Hardware Modification on Board to Allow Different
Modulation Schemes
Low Standby Current: 50 µA at 3V, 25°C
ASK/FSK Receiver Uses a Low-IF Architecture With High Selectivity, Blocking, and
Low Intermodulation (Typical 3-dB Blocking 68.0 dBC at ±3 MHz/74.0 dBC at
±20.0 MHz, System I1dBCP = –31 dBm/System IIP3 = –24 dBm)
Telegram Pause Up to 52 ms Supported in ASK Mode
Wide Bandwidth AGC to Handle Large Out-of-band Blockers above the System I1dBCP
440-kHz IF Frequency With 30-dB Image Rejection and 420-kHz IF Bandwidth to
Support PLL Transmitters With Standard Crystals or SAW-based Transmitters
RSSI (Received Signal Strength Indicator) With Output Signal Dynamic Range of 65 dB
Low In-band Sensitivity Change of Typically ±2.0 dB Within ±160-kHz Center
Frequency Change in the Complete Temperature and Supply Voltage Range
Sophisticated Threshold Control and Quasi-peak Detector Circuit in the Data Slicer
Fast and Stable XTO Start-up Circuit (> –1.4 k Worst-case Start Impedance)
Clock Generation for Microcontroller
ESD Protection at all Pins (±4 kV HBM, ±200V MM, ±500V FCDM)
Dual Supply Voltage Range: 2.7V to 3.3V or 4.5V to 5.5V
Temperature Range: –40°C to +85°C
Small 5 mm
5 mm QFN24 Package
Applications
Industrial/Aftermarket Keyless Entry and Tire Pressure Monitoring Systems
Alarm, Telemetering and Energy Metering Systems
Remote Control Systems for Consumer and Industrial Markets
Access Control Systems
Home Automation
Home Entertainment
Toys
-3
)
-3
)
-3
)
-3
)
UHF ASK/FSK
Receiver
ATA8201
ATA8202
4971C–INDCO–04/09

ATA8202-PXQW Summary of contents

  • Page 1

    ... Features • Transparent RF Receiver ICs for 315 MHz (ATA8201) and 433.92 MHz (ATA8202) With High Receiving Sensitivity • Fully Integrated PLL With Low Phase Noise VCO, PLL, and Loop Filter • High FSK/ASK Sensitivity:–105 dBm (ATA8201, FSK, 9.6 Kbits/s, Manchester, BER 10 – ...

  • Page 2

    ... Allows a Low-cost Application With Only 8 Passive Components • Optimal Bandwidth Maximizes Sensitivity while Maintaining SAW Transmitter Compatibility • Clock Output Provides an External Microcontroller Crystal-precision Time Reference • Well Suited for Use With PLL Transmitter ATA8401/ATA8402/ATA8403/ATA8404/ATA8405 ATA8201/ATA8202 Printed-loop Antennas 4971C–INDCO–04/09 ...

  • Page 3

    ... Because of the highly integrated design, the only required RF components are for the purpose of receiver antenna matching. ATA8201 and ATA8202 support Manchester bit rates of 1 Kbit Kbits/s in ASK and 1 Kbit Kbits/s in FSK mode. The four discrete bit rate passbands are selectable and cover 1 ...

  • Page 4

    ... VS3V_AVCC 12 GND 13 LNA_GND 14 LNA_IN 15 SENSE 16 SENSE_CTRL 17 RSSI 18 TEST3 BR0 21 BR1 22 ASK_NFSK 23 CDEM 24 DATA_OUT GND ATA8201/ATA8202 TEST2 1 18 TEST1 2 17 CLK_OUT 3 16 CLK_OUT_CTRL1 4 15 CLK_OUT_CTRL0 5 14 ENABLE Function Test pin, during operation at GND Test pin, during operation at GND Output to clock a connected microcontroller ...

  • Page 5

    ... Figure 1-3. 4971C–INDCO–04/09 Block Diagram ASK/FSK CDEM Demo- dulator IF Amp SENSE SENSE_CTRL IF Filter GND LPF DVCC IF Amp LPF LNA_IN LNA LNA_GND ATA8201/ATA8202 ASK VS3V_AVCC Power Supply VS5V FSK ASK/FSK ASK_NFSK Control Data DATA_OUT Slicer BR0 BR1 Standby RX Logic Control CLK_OUT_CTRL1 ...

  • Page 6

    ... RKE and TPM systems. A benefit of the integrated receive fil- ter is that no external components needed. At 315 MHz, the ATA8201 receiver (433.92 MHz for the ATA8202 receiver) has a typical system noise figure of 6.0 dB (7.0 dB), a system I1dBCP of –31 dBm (–30 dBm), and a system IIP3 of – ...

  • Page 7

    ... ATA8201/ATA8202 (RF_IN In_p 1300 //1.60 (55 – j216) 900 //1.60 Figure 2-1 Table 2-2. The reflection coefficients were always Table 2-3 and Table 2-4 on page / R In_p loss ATA8201/ATA8202 14 LNA_IN L1 L [nH //C [pF] In_p and the val- 8. These measure- Table 2- ...

  • Page 8

    ... IF-filter bandwidth of the receiver. page 9 Figure 2-4 and 9.6 Kbits/s, ±38 kHz, Manchester versus the frequency offset between transmitter and receiver at T ATA8201/ATA8202 8 BR_Range_0 BR_Range_1 2.5 Kbits/s 5 Kbits/s – ...

  • Page 9

    ... RF (kHz) at 315 MHz ATA8201/ATA8202 0 100 200 300 0 100 200 300 9 ...

  • Page 10

    ... Figure 2-4. Figure 2-5. ATA8201/ATA8202 10 Measured Sensitivity (315 MHz, FSK, 2.4 Kbits/s, ±38 kHz, Manchester) Versus Frequency Offset Input Sensitivity (dBm) at BER < 1e-3, ATA8201, FSK, 2.4 Kbits/s (Manchester), BR0 -112.00 -111.00 -110.00 -109.00 -108.00 -107.00 -106.00 -105.00 -104.00 -103.00 -102.00 -101.00 -100 ...

  • Page 11

    ... Figure 2-5 on page 10, the supply voltage has almost no influence. The tem- For the demodulator used in the ATA8201/ATA8202, the tolerable frequency offset does not change with the data frequency. Hence, the value of ±160 kHz is valid for 1 Kbit Kbits/s. 1 0). ...

  • Page 12

    ... BER is higher than 10 The measurements were done at the 50 input shown –102 dBm + 67.5 dBC = –34.5 dBm. Figure 2-6. Figure 2-7. ATA8201/ATA8202 12 Figure 2-6 on page 2-6, and Figure 2-7 on page 12 show the narrow-band blocking, and ...

  • Page 13

    ... Table 2-8. The ATA8201/ATA8202 can also receive FSK and ASK modulated signals if they are much higher than the I1dBCP. It can typically receive useful signals the nonlinear dynamic range (that is, the maximum to minimum receiving signal), and for 10 Kbits/s Manchester (FSK) ...

  • Page 14

    ... IF filter. Hence, the demod- ulator, data filter, and data slicer are important. The data filter of the ATA8201/ATA8202 functions also as a quasi-peak detector. This results in a good suppression of above mentioned disturbers and exhibits a good carrier-to-noise perfor- mance ...

  • Page 15

    ... The divided frequency is compared to f current output of the phase frequency detector is connected to the fully integrated loop filter, and thereby generates the control voltage for the VCO. By means of that configuration, the VCO is ...

  • Page 16

    ... High if the amplitude is large enough; this activates the CLK_OUT output enabled via the pins CLK_OUT_CTRL0 and CLK_OUT_CTRL1. Note that the necessary conditions of the DVCC voltage also have to be fulfilled recommended to use a crystal with 1 2.2 pF. 0 Lower values of C higher values of C ATA8201/ATA8202 16 10 fF, C 1.0 pF and the XTAL has to be lower than C ...

  • Page 17

    ... PCB. The supply voltage of the microcontroller must also be carefully blocked. 4971C–INDCO–04/09 XTO Block Diagram XTAL1 XTAL2 CLK_OUT_CTRL0 and the f XTO RF Calculation Frequency [MHz] 433.92 (ATA8202) 315.0 (ATA8201) ATA8201/ATA8202 CLK_OUT_CTRL1 CLK_OUT f Divider FXTO /3, /6, /12 Amplitude Detector Divider f /16 DCLK is shown in Table 3-1 ...

  • Page 18

    ... Debouncing of the data signal stream - Start-up time of the RX signal path The start-up time and the debounce characteristic depend on the selected bit rate range (BR_Range) which is defined by pins BR0 and BR1. The clock cycle T lowing formulas for further reference: BR_Range ATA8201/ATA8202 18 Setting of f CLK_OUT CLK_OUT_CTRL0 0 ...

  • Page 19

    ... R Figure 10-1 on page Figure 2-1 on page 7 (defined by the external resistor R Th_red , and from then on the data stream will be available on pin Th_red Figure 4-2 on page ATA8201/ATA8202 . R is connected between Sense Sense 29). The output of the comparator , the maximum sensitivity by the sig- Sense and exhibits the best possible sensitivity ...

  • Page 20

    ... Figure 4-1. Figure 4-2. ATA8201/ATA8202 20 Reduced Sensitivity Active ENABLE ASK_NFSK SENSE_CTRL RX V Th_red RSSI t t Startup_PLL Startup_Sig_Proc DATA_OUT Restart Reduced Sensitivity ENABLE ASK_NFSK SENSE_CTRL RX V Th_red RSSI t Startup_Sig_Proc DATA_OUT 4971C–INDCO–04/09 ...

  • Page 21

    ... Figure 5-1. VS3V_AVCC The supply voltage range of the ATA8201/ATA8202 is 2.7V to 3.3V or 4.5V to 5.5V. Pin VS3V_AVCC is the supply voltage input for the range 2.7V to 3.3V, and is used in battery applications using a single lithium 3V cell. Pin VS5V is the voltage input for the range 4.5V to 5.5V (car applications) in this case the voltage regulator V_REG regulates VS3V_AVCC to typi- cally 3.0V. If the voltage regulator is active, a blocking capacitor of 2.2 µ ...

  • Page 22

    ... Table 5-3. During T circuit starts up (T ready to receive. The duration of the start-up sequence depends on the selected bit rate range. Figure 5-3. Active Mode CLK_OUT ENABLE RX DATA_OUT I Standby Standby Mode ATA8201/ATA8202 22 Standby Mode RX ENABLE XTO_Startup Active Mode RX ENABLE 1 1 the PLL is enabled and starts up. If the PLL is locked, the signal processing Startup_PLL ) ...

  • Page 23

    ... Table 5-4. BR1 Table 5-5. ASK_NFSK 4971C–INDCO–04/09 Start-up Time ATA8202 (433.92 MHz) BR0 T T Startup_PLL Startup_Sig_Proc 0 1 261 µ Modulation Scheme RF at Pin LNA_IN IN f FSK_H 0 f FSK_L f on ASK 1 f off ASK ATA8201/ATA8202 ATA8201 (315 MHz) T Startup_PLL 1096 µs 644 µ ...

  • Page 24

    ... To ensure an accurate settling of the data filter during the start-up period ( time T of the data signal (preamble) must be inside the given limits during this period. EE ATA8201/ATA8202 24 26). Each BR_Range is defined by a minimum edge-to-edge time. To maintain full sen- Minimum Edge-to-edge Recommended Bit Rate ...

  • Page 25

    ... Logic 0 PWM: Logic 0 VPWM: On Transition Low to High On Transition High to Low PPM: Logic 0 NRZ: Logic 0 Figure 6-2. Supported Header and Blanking Periods Preamble 4971C–INDCO–04/ Logic Logic 1 Logic Logic Logic Logic 1 Header Data Burst Guard Time ATA8201/ATA8202 Logic Logic Data Burst 25 ...

  • Page 26

    ... ASK Preamble 2.4 Kbits/s followed by FSK Data 9.6 Kbits/s ENABLE RX BR1 BR0 ASK_NFSK DATA_OUT Data valid BR0 ATA8201/ATA8202 26 ) depends on the bit rate range being selected (not current bit Startup_Sig_Proc Table 5-4 on page 23. This response time is specified for applications , the level on pin DATA_OUT is low. T ...

  • Page 27

    ... Kbits/s, T --> T Startup_PLL --> T Startup_Sig_Proc --> T Bitcheck 3V application; ASK mode, CLK_OUT disabled --> I Startup_PLL --> I Active --> I Standby --> 0.545 mA Polling ATA8201/ATA8202 I Standby (Startup Signal Processing Startup_PLL Startup_Sig_Proc Polling_Period – T – T Startup_PLL Startup_Sig_Proc = 269 µs = 324 µs ...

  • Page 28

    ... Application Figure 9-1. 3V Application output output output output input output VSS VCC Note: ATA8201/ATA8202 TEST2 TEST1 ATA8201/ CLK_OUT ATA8202 CLK_OUT_CTRL1 CLK_OUT_CTRL0 ENABLE 2.7V to 3.3V CC Paddle (backplane) must be connected to GND TEST3 RSSI SENSE_CTRL SENSE RF 2 LNA_IN 68 nH/36 nH LNA_GND 315 MHz/433.92 MHz 68 nF 4971C– ...

  • Page 29

    ... VSS VCC Note: 4971C–INDCO–04/ TEST2 TEST1 ATA8201/ CLK_OUT ATA8202 CLK_OUT_CTRL1 CLK_OUT_CTRL0 ENABLE 4.5V to 5.5V CC Paddle (backplane) must be connected to GND ATA8201/ATA8202 TEST3 RSSI SENSE_CTRL R Sense SENSE 2.2 pF LNA_IN RF IN LNA_GND 68 nH/36 nH 315 MHz/433.92 MHz 2.2 µF 29 ...

  • Page 30

    ... CLK_OUT disabled XTO startup 2.3 System start-up time XTAL Type means 100% tested 100% correlation tested Characterized on samples Design parameter Note: 1. Pin numbers in parenthesis were measured with RF_IN matched to 50 according to values as in Table 2-2 on page 7 ATA8201/ATA8202 30 Symbol stg T amb V S HBM ...

  • Page 31

    ... P REF_FSK (14) P REF_FSK (14) P REF_FSK (14) P REF_FSK – 25°C (14) P REF_ASK (14) P REF_ASK ( ATA8201/ATA8202 = 3V, and V = 5V. Typical values are given at VS5V Min. Typ. Max. + 6.5 Active 6.7 Active 6.7 Active 6.9 Active 545 Polling –103 –105 –106.5 –106 –108 –109.5 – ...

  • Page 32

    ... RF 3.10 System noise figure Type means 100% tested 100% correlation tested Characterized on samples Design parameter Note: 1. Pin numbers in parenthesis were measured with RF_IN matched to 50 according to values as in Table 2-2 on page 7 ATA8201/ATA8202 32 = 25° amb VS3V_AVCC VS5V (1) Pin Symbol = 315 MHz to = 433 ...

  • Page 33

    ... 315 MHz (14) = 433.92 MHz (14) – 3 with any (14) SNR (14) SNR < (14) SNR RF RFIN_High ( ATA8201/ATA8202 = 3V, and V = 5V. Typical values are given at VS5V Min. Typ. f 440 IF f 440 IF SBW 435 IIP3 –24 IIP3 –23 –31 –30 Z (72.4 – j298) in_LNA Z (55 – j216) ...

  • Page 34

    ... MHz Capacitor connected to 3.23 CDEM pin 23 (CDEM) *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter Note: 1. Pin numbers in parenthesis were measured with RF_IN matched to 50 according to values as in Table 2-2 on page 7 ATA8201/ATA8202 34 = 25° amb VS3V_AVCC VS5V (1) Pin ...

  • Page 35

    ... 7,8 V 7,8 V 2.2 pF, small signal 7,8 Z XTAL12_START 2.2 pF 7,8 < 433.92 MHz 7,8 = 315 MHz ATA8201/ATA8202 = 3V, and V = 5V. Typical values are given at VS5V Min. Typ XTO 300 C 0max f –5 XTO 700 PPXTAL 350 PPXTAL –1400 –2000 R 15 m_max 13.57375 ...

  • Page 36

    ... Used for current 6.2 capacitance calculation *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter Note: 1. Pin numbers in parenthesis were measured with RF_IN matched to 50 according to values as in Table 2-2 on page 7 ATA8201/ATA8202 36 = 25° amb VS3V_AVCC VS5V (1) Pin Symbol = 433 ...

  • Page 37

    ... VS5V Pin Symbol = V 3V VS5V 10 SOFF V VS3V_AVCC 10 VS5V = V 3V VS5V 10 Standby = V 3V VS5V 10 Startup_PLL = V 3V VS5V 10 Active = V 3V VS5V 10 Active ATA8201/ATA8202 = 5V. Typical values are given at VS5V Min. Typ. Max. Unit 2 µA , 2.7 3.3 V 420 µA 290 220 50 4.5 mA 6.5 mA 6.7 mA Type ...

  • Page 38

    ... CLK disabled Startup_PLL V Current in Active 8.5 CLK disabled mode ASK SENSE_CTRL = 0 V Current in Active 8.6 CLK disabled mode FSK SENSE_CTRL = 0 *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter ATA8201/ATA8202 38 = 25° amb VS3V_AVCC VS5V Pin Symbol = 5V VS5V VS5V ...

  • Page 39

    ... Type means 100% tested 100% correlation tested Characterized on samples Design parameter 4971C–INDCO–04/09 = 25° 3V, and V amb VS3V_AVCC VS5V Pin Symbol T DCLK T XDCLK T Startup_PLL T Startup_Sig_Proc BR_Range 24 T DATA_OUT_min T DATA_OUT ATA8201/ATA8202 = 5V. Typical values are given at VS5V Min. Typ. Max. Unit µs XTO XTO µ DCLK DCLK 15 µ ...

  • Page 40

    ... V ASK_NFSK input VS5V - Low level input voltage V S 4.5V to 5.5V 11 VS5V - High level input voltage V S 4.5V to 5.5V *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter ATA8201/ATA8202 40 = 25° amb VS3V_AVCC VS5V Pin Symbol = V = VS3V_AVCC = 2. VS5V ...

  • Page 41

    ... VS3V_AVCC = 2. VS5V = V = VS3V_AVCC = 2. VS5V = V = VS3V_AVCC = 2. VS5V = V = VS3V_AVCC = 2. VS5V = V = VS3V_AVCC = 2. VS5V = V = VS3V_AVCC = 2. VS5V ATA8201/ATA8202 = 3V, and V = 5V. Typical values are given at VS5V Min. Typ. Max Unit Type ...

  • Page 42

    ... CLK_OUT output Saturation voltage low 4.5V to 5.5V I DATA_OUT 11. VS5V - Saturation voltage high V S 4.5V to 5.5V I DATA_OUT *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter ATA8201/ATA8202 42 = 25° amb VS3V_AVCC VS5V Pin Symbol = V = VS3V_AVCC = 2. VS5V = 250 µA ...

  • Page 43

    ... Ordering Information Extended Type Number ATA8202-PXQW ATA8201-PXQW 19. Package Information Package: QFN Exposed pad 3.6 x 3.6 (acc. JEDEC OUTLINE No. MO-220) Dimensions in mm Not indicated tolerances ±0. Drawing-No.: 6.543-5122.01-4 Issue: 1; 15.11.05 20. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document ...

  • Page 44

    ... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...