ISP1504CBS NXP Semiconductors, ISP1504CBS Datasheet
ISP1504CBS
Specifications of ISP1504CBS
Available stocks
Related parts for ISP1504CBS
ISP1504CBS Summary of contents
Page 1
IMPORTANT NOTICE Dear customer from August 2 2008, the wireless operations of NXP have moved to a new company, ST-NXP Wireless result, the following changes are applicable to the attached document. ● Company name - NXP ...
Page 2
ISP1504A; ISP1504C ULPI Hi-Speed Universal Serial Bus On-The-Go transceiver Rev. 03 — 7 April 2008 1. General description The ISP1504 is a Universal Serial Bus (USB) On-The-Go (OTG) transceiver that is fully compliant with Universal Serial Bus Specification Rev. 2.0 ...
Page 3
... N 60 MHz, 8-bit interface between the core and the transceiver N Supports 60 MHz output clock configuration N Integrated Phase-Locked Loop (PLL) supporting one crystal or clock frequency: 19.2 MHz (ISP1504ABS) and 26 MHz (ISP1504CBS) N Fully programmable ULPI-compliant register set N Internal Power-On Reset (POR) circuit I ...
Page 4
... Part Type number Marking Crystal or clock frequency [1] ISP1504ABS 504A 19.2 MHz [1] ISP1504CBS 504C 26 MHz [1] The package marking is the first line of text on the IC package and can be used for IC identification. ISP1504A_ISP1504C_3 Product data sheet Package Name Description HVQFN32 plastic thermal enhanced very thin quad flat package; ...
Page 5
... NXP Semiconductors 5. Block diagram 27 CLOCK 26, 8 28, 31, 32 DATA [7:0] ULPI INTERFACE 19 DIR 20 STP 21 NXT 29 CHIP_SELECT_N 17 RESET_N 15 XTAL1 16 XTAL2 2, 22, 30 interface voltage V CC(I/O) 14 REG3V3 18 REG1V8 Fig 1. Block diagram ISP1504A_ISP1504C_3 Product data sheet USB DATA SERIALIZER ULPI INTERFACE CONTROLLER USB DATA DESERIALIZER DRV V ...
Page 6
... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. 6.2 Pin description Table 2. Pin description [1][2] Symbol Pin Type DATA0 1 I CC(I/O) RREF AI/O FAULT CPGND 8 P C_B 9 AI/O C_A 10 AI PSW_N 12 OD ISP1504A_ISP1504C_3 Product data sheet terminal 1 index area DATA0 CC(I/O) ...
Page 7
... NXP Semiconductors Table 2. Pin description …continued [1][2] Symbol Pin Type V 13 AI/O BUS REG3V3 14 P XTAL1 15 AI XTAL2 16 AO RESET_N 17 I REG1V8 18 P DIR 19 O STP 20 I NXT CC(I/O) DATA7 23 I/O DATA6 24 I/O DATA5 25 I/O DATA4 26 I/O CLOCK 27 O DATA3 28 I/O ...
Page 8
... NXP Semiconductors 7. Functional description 7.1 ULPI interface controller The ISP1504 provides a 12-pin interface that is compliant with UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 . This interface must be connected to the USB link. The ULPI interface controller provides the following functions: • ...
Page 9
... NXP Semiconductors • Differential and single-ended receivers to receive data at high-speed, full-speed and low-speed • Squelch circuit to detect high-speed bus activity • High-speed disconnect detector • 45 • 1.5 k pull-up resistor on DP for full-speed peripheral mode • bus terminations on DP and DM for host and OTG modes For details on controlling resistor settings, see 7 ...
Page 10
... NXP Semiconductors • Resistors to temporarily charge and discharge V • Charge pump to provide 5 V power on V power from the ISP1504 V 7.6.1 ID detector The ID detector detects which end of the micro-USB cable is plugged in. The detector must first be enabled by setting the ID_PULLUP register bit to logic 1. If the ISP1504 senses a value on ID that is different from the previously reported value, an RXCMD status update will be sent to the USB link interrupt will be asserted ...
Page 11
... NXP Semiconductors 7.6.4 Charge pump The ISP1504 uses a built-in charge pump to supply current The charge pump works as a capacitive DC-DC converter. An external holding capacitor, C which also shows a typical OTG V amount of current drive required. If the internal charge pump is not used, the C capacitor is not required. ...
Page 12
... NXP Semiconductors 7.9.2 V CC(I/O) The input power pin that sets the I/O voltage level. For details, see and Section • CHIP_SELECT_N • CLOCK • DATA[7:0] • DIR • NXT • RESET_N • STP 7.9.3 RREF Resistor reference analog I/O pin. A resistor, R and GND, as shown in biases internal analog circuitry ...
Page 13
... NXP Semiconductors 7.9.8 C_A and C_B The C_A and C_B pins are to connect the flying capacitor of the charge pump. The output current capability of the charge pump depends on the value of the capacitor used, as shown in For details, see If the charge pump is not used, C_A and C_B must be left floating (not connected). ...
Page 14
... NXP Semiconductors To prevent electrical overstress strongly recommended that you attach a series resistor on the V internal charge pump. For details, see 7.9.12 REG3V3 and REG1V8 Regulator output voltage. These supplies are used to power the ISP1504 internal digital and analog circuits, and must not be used to power external circuits. ...
Page 15
... NXP Semiconductors 7.9.16 STP ULPI stop input pin. The link must assert STP to signal the end of a USB transmit packet or a register write operation. When DIR is asserted, the link can optionally assert STP to abort the ISP1504, causing it to deassert DIR in the next clock cycle. A weak pull-up resistor is incorporated into the STP pin as part of the interface protect feature ...
Page 16
... NXP Semiconductors 8. Modes of operation 8.1 ULPI modes The ISP1504 ULPI bus can be programmed to operate in four modes. Each mode reconfigures the signals on the data bus as described in the following subsections. Setting more than one mode will lead to undefined behavior. 8.1.1 Synchronous mode This is default mode ...
Page 17
... NXP Semiconductors Table 4. Signal name DIR STP NXT 8.1.2 Low-power mode When the USB is idle, the link can place the ISP1504 into low-power mode (also called suspend mode). In low-power mode, the data bus definition changes to that shown in Table 5. To enter low-power mode, the link sets the SUSPENDM bit in the Function Control register to logic 0 ...
Page 18
... NXP Semiconductors Table 5. Signal mapping during low-power mode Signal Maps to Reserved DATA2 INT DATA3 Reserved DATA[7:4] 8.1.3 6-pin full-speed or low-speed serial mode If the link requires a 6-pin serial interface to transmit and receive full-speed or low-speed USB data, it can set the ISP1504 to 6-pin serial mode. In 6-pin serial mode, the DATA[7:0] bus defi ...
Page 19
... NXP Semiconductors Table 7. Signal mapping for 3-pin serial mode Signal Maps to TX_ENABLE DATA0 DAT DATA1 SE0 DATA2 INT DATA3 Reserved DATA[7:4] 8.2 USB and OTG state transitions A Hi-Speed USB peripheral, host or OTG device handles more than one electrical state as defined in Universal Serial Bus Specification Rev. 2.0 and On-The-Go Supplement to the USB 2.0 Specifi ...
Page 20
... NXP Semiconductors Table 8. Operating states and their corresponding resistor settings Signaling mode Register settings XCVR SELECT [1:0] Host low-speed 10b suspend Host low-speed 10b resume Host Test J or Test K 00b Peripheral settings Peripheral chirp 00b Peripheral 00b high-speed Peripheral full-speed 01b ...
Page 21
... NXP Semiconductors 9. Protocol description The following subsections describe the protocol for using the ISP1504. 9.1 ULPI references The ISP1504 provides a 12-pin ULPI interface to communicate with the link highly recommended that you read UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 and UTMI+ Specifi ...
Page 22
... NXP Semiconductors If a crystal is attached or a clock is driven into the XTAL1 pin, the ISP1504 will drive a 60 MHz clock out from the CLOCK pin when DIR deasserts. This is shown as CLOCK in Figure 6. The recommended power-up sequence for the link is as follows: 1. The link waits for 1 ms, ignoring all the ULPI pin status. ...
Page 23
... NXP Semiconductors CC(I/O) REG1V8 t PWRUP internal REG1V8 detector internal POR XTAL1 CLOCK DATA[7:0] DIR STP NXT and V are applied to the ISP1504. The ISP1504 regulator starts to turn on. CC CC(I/ ULPI pads detect REG1V8 rising above the REG1V8 regulator threshold and are not in 3-state. These pads may drive either LOW or HIGH recommended that the link ignores the ULPI pins status during The POR threshold is reached and a POR pulse is generated. After the POR pulse, ULPI pins are driven to a defi ...
Page 24
... NXP Semiconductors The interface protect feature can be disabled by setting the INTF_PROT_DIS bit to logic 1. 9.3.2 Interface behavior with respect to RESET_N The use of the RESET_N pin is optional. When RESET_N is asserted (LOW), the ISP1504 will assert DIR. All logic in the ISP1504 will be reset, including the analog circuitry and ULPI registers. During reset, the link must drive DATA[7:0] and STP to LOW ...
Page 25
... NXP Semiconductors entering 3-state mode CLOCK CHIP_ SELECT_N DATA[7:0] DIR NXT STP Fig 8. Entering and exiting 3-state in normal mode CLOCK CHIP_ SELECT_N DATA[7:0] TXCMD DIR NXT STP SUSPENDM Remark: Clock timing is not to scale. Fig 9. Entering and exiting 3-state in suspend mode ISP1504A_ISP1504C_3 ...
Page 26
... NXP Semiconductors 9.4 V power and fault detection BUS 9.4.1 Driving The ISP1504 provides a built-in charge pump. To enable the charge pump, the link must set the DRV_VBUS bit in the OTG Control register. The ISP1504 also supports external 5 V supplies. The ISP1504 can control the external supply using the active-LOW PSW_N open-drain output pin ...
Page 27
... NXP Semiconductors Table 10. TXCMD byte format Command Command code type name DATA[7:6] Idle 00b Packet 01b transmit Register 10b write Register read 11b 9.5.2 RXCMD The ISP1504 communicates status information to the link by asserting DIR and sending an RXCMD byte on the data bus. The RXCMD data byte format is given in The ISP1504 will automatically send an RXCMD whenever there is a change in any of the RXCMD data fi ...
Page 28
... NXP Semiconductors CLOCK turnaround DATA [ 7:0 ] DIR STP NXT Fig 10. Single and back-to-back RXCMDs from the ISP1504 to the link 9.5.2.1 Linestate encoding LINESTATE[1:0] reflects the current state of DP and DM. Whenever the ISP1504 detects a change DM, an RXCMD will be sent to the link with the new LINESTATE[1:0] value ...
Page 29
... NXP Semiconductors Table 13. LINESTATE[1:0] encoding for downstream facing ports: host DP_PULLDOWN and DM_PULLDOWN = 1. Mode Low-speed XCVRSELECT[1:0] 10 TERMSELECT 1 OPMODE[1:0] X LINESTATE[1:0] 00 SE0 01 LS-K 10 LS-J 11 SE1 [1] !squelch indicates inactive squelch. !HS_Differential_Receiver_Output indicates inactive HS_Differential_Receiver_Output. 9.5.2.2 V state encoding BUS USB devices must monitor the V starting a session and SRP. The V ...
Page 30
... NXP Semiconductors USE_EXT_VBUS_IND, IND_PASSTHRU Fig 11. RXCMD A_VBUS_VLD indicator source 9.5.2.3 Using and selecting the V The V BUS link whenever there is a change in the V must first enable the corresponding interrupts in the USB Interrupt Enable Rising Edge and USB Interrupt Enable Falling Edge registers. ...
Page 31
... NXP Semiconductors OTG devices: provide a minimum there is no need for an overcurrent detection circuit because the internal A_VBUS_VLD comparator is sufficient. If the OTG A-device provides more than 100 overcurrent detector must be used and 29 applies. The OTG A-device also uses SESS_VLD to detect when an OTG A-device is initiating V When an OTG device is confi ...
Page 32
... NXP Semiconductors 9.6 Register read and write operations Figure 12 addressing and extended addressing register operations. Extended register addressing is optional for links. Note that register operations will be aborted if the ISP1504 unexpectedly asserts DIR during the operation. When a register operation is aborted, the link must retry until successful. For more information on register operations, refer to UTMI+ Low Pin Interface (ULPI) Specifi ...
Page 33
... NXP Semiconductors than 7 ms after reset time T up its clock within 5.6 ms, leaving 200 s for the link to start transmitting the Chirp K, and 1.2 ms for the Chirp K to complete (worst case with 10 % slow clock). b. Host chirp: If the host does not detect the peripheral chirp, it must continue asserting SE0 until the end of reset ...
Page 34
... NXP Semiconductors USB reset T 0 TXCMD (REGW) SE0 DATA [ 7:0 ] DIR STP NXT 01 (FS) XCVR SELECT TERM SELECT 00 (normal) OP MODE J (01b) SE0 (00b) LINE STATE TXCMD SE0 (REGW) DATA [ 7:0 ] DIR STP NXT 01 (FS) XCVR SELECT TERM SELECT 00 (normal) OP MODE J (01b) ...
Page 35
... NXP Semiconductors 9.8 USB packet transmit and receive An example of a packet transmit and receive is shown in packets, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 . link sends TXCMD CLOCK DATA [ 7:0 ] TXCMD DIR STP NXT Fig 14. Example of using the ISP1504 to transmit and receive USB data 9 ...
Page 36
... NXP Semiconductors Table 18. Link decision times Packet sequence High-speed link delay Transmit-Transmit (host only) Receive-Transmit (host or peripheral) Receive-Receive 1 (peripheral only) Transmit-Receive 92 (host or peripheral DATA DM CLOCK DATA [7:0] DIR STP NXT TX end delay (two to five clocks) Fig 15. High-speed transmit-to-transmit packet timing ISP1504A_ISP1504C_3 ...
Page 37
... NXP Semiconductors DP or DATA EOP DM CLOCK DATA [7: DIR STP NXT RX end delay (three to eight clocks) Fig 16. High-speed receive-to-transmit packet timing 9.9 Preamble Preamble packets are headers to low-speed packets that must travel over a full-speed bus, between a host and a hub. To enter preamble mode, the link sets XCVRSELECT[1:0] = 11b in the Function Control register ...
Page 38
... NXP Semiconductors CLOCK DATA[7: Fig 17. Preamble sequence 9.10 USB suspend and resume 9.10.1 Full-speed or low-speed host-initiated suspend and resume Figure 18 suspend and sometime later initiates resume signaling to wake up the downstream peripheral. Note that LINESTATE updates. The sequence of events for a host and a peripheral, both with ISP1504 follows: 1 ...
Page 39
... NXP Semiconductors idle DATA [ 7:0 ] DIR STP NXT OPMODE 00b LINE STATE CLOCK TXCMD (REGW) DATA [ 7:0 ] DIR STP NXT OPMODE SUSPENDM LINE STATE DP DM Timing is not to scale. Fig 18. Full-speed suspend and resume 9.10.2 High-speed suspend and resume Figure 19 suspend and then initiates resume signaling. The high-speed peripheral will wake up and return to high-speed operations ...
Page 40
... NXP Semiconductors The sequence of events related to a host and a peripheral, both with ISP1504 follows: 1. High-speed idle: Initially, the host and the peripheral are idle. The host has its 15 k pull-down resistors enabled (DP_PULLDOWN and DM_PULLDOWN are set to 1b) and Full-speed suspend: When the peripheral sees no bus activity for 3 ms, it enters the suspend state ...
Page 41
... NXP Semiconductors HS idle TXCMD (REGW) DATA [ 7:0 ] DIR STP NXT XCVR 00b SELECT TERM SELECT OP MODE !SQUELCH SQUELCH (00b) (01b) LINE STATE CLOCK TXCMD (REGW) DATA [ 7:0 ] DIR STP NXT XCVR 00b SELECT TERM SELECT OP MODE SUSPENDM !SQUELCH SQUELCH (01b) (00b) ...
Page 42
... NXP Semiconductors 9.10.3 Remote wake-up The ISP1504 supports peripherals that initiate remote wake-up resume. When placed into USB suspend, the peripheral link remembers at what speed it was originally operating. Depending on the original speed, the link follows one of the protocols detailed here. In Figure 20, timing is not to scale, and not all RXCMD LINESTATE updates are shown ...
Page 43
... NXP Semiconductors LINESTATE DATA [ 7:0 ] DIR STP NXT XCVR SELECT TERM SELECT OP MODE TXCMD LINESTATE REGW DATA [ 7:0 ] DIR STP NXT XCVR SELECT TERM SELECT OP MODE Timing is not to scale. Fig 20. Remote wake-up from low-power mode 9.11 No automatic SYNC and EOP generation (optional) This setting allows the link to turn off the automatic SYNC and EOP generation, and must be used for high-speed packets only ...
Page 44
... NXP Semiconductors PHY will not transmit any EOP. The ISP1504 will also detect if the PID byte is A5h, indicating an SOF packet, and automatically send a long EOP when STP is asserted. To transmit chirp and resume signaling, the link must set OPMODE to 10b. CLOCK TXCMD ...
Page 45
... NXP Semiconductors 9.12.1 OTG charge pump A description of the charge pump is given in configured as an A-device, it can provide the V Control of the charge pump is described in 9.12.2 OTG comparators The ISP1504 provides comparators that conform to On-The-Go Supplement to the USB 2.0 Specification Rev. 1.3 requirements of V ...
Page 46
... NXP Semiconductors SYNC DATA0 (TX_ENABLE) DATA1 (TX_DAT) DATA2 (TX_SE0) DATA4 (RX_DP) DATA5 (RX_DM) DATA6 (RX_RCV Fig 22. Example of transmit followed by receive in 6-pin serial mode SYNC DATA0 (TX_ENABLE) DATA1 (TX_DAT/ RX_RCV) DATA2 (TX_SE0/ RX_SE0 Fig 23. Example of transmit followed by receive in 3-pin serial mode ISP1504A_ISP1504C_3 Product data sheet ISP1504A ...
Page 47
... NXP Semiconductors 9.14 Aborting transfers The ISP1504 supports aborting transfers on the ULPI bus. For details, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1, Section 3.8.4 . 9.15 Avoiding contention on the ULPI data bus Because the ULPI data bus is bidirectional, avoid situations in which both the link and the PHY simultaneously drive the data bus ...
Page 48
... NXP Semiconductors 10. Register map Table 19. Immediate register set overview Field name Vendor ID Low register Vendor ID High register Product ID Low register Product ID High register Function Control register Interface Control register OTG Control register USB Interrupt Enable Rising Edge register USB Interrupt Enable Falling Edge ...
Page 49
... NXP Semiconductors 10.1 Immediate register set 10.1.1 Vendor ID and Product ID registers 10.1.1.1 Vendor ID Low register Table 21 Table 21. Vendor ID Low register (address R = 00h) bit description Bit Symbol Access VENDOR_ID_ R LOW[7:0] 10.1.1.2 Vendor ID High register The bit description of the register is given in Table 22. ...
Page 50
... NXP Semiconductors Table 26. Function Control register (address R = 04h to 06h 04h 05h 06h) bit description Bit Symbol Description 7 - reserved 6 SUSPENDM Suspend LOW: Active LOW PHY suspend. Places the PHY into low-power mode. The PHY will power down all blocks, except the full-speed receiver, OTG comparators and ULPI interface pins. ...
Page 51
... NXP Semiconductors Table 28. Interface Control register (address R = 07h to 09h 07h 08h 09h) bit description Bit Symbol Description 7 INTF_PROT_DIS Interface Protect Disable: Controls circuitry built into the ISP1504 to protect the ULPI interface when the link 3-states STP and DATA[7:0]. When this bit is enabled, the ISP1504 will automatically detect when the link stops driving STP. 0b — ...
Page 52
... NXP Semiconductors Table 29. OTG Control register (address R = 0Ah to 0Ch 0Ah 0Bh 0Ch) bit allocation Bit 7 Symbol USE_EXT_ DRV_ VBUS_IND VBUS_EXT Reset 0 Access R/W/S/C R/W/S/C Table 30. OTG Control register (address R = 0Ah to 0Ch 0Ah 0Bh 0Ch) bit description Bit Symbol Description 7 USE_EXT_VBUS_ Use External V IND 0b — ...
Page 53
... NXP Semiconductors 10.1.5 USB Interrupt Enable Rising Edge register The bits in this register enable interrupts and RXCMDs to be sent when the corresponding bits in the USB Interrupt Status register change from logic 0 to logic 1. By default, all transitions are enabled. Table 31. ...
Page 54
... NXP Semiconductors Table 34. USB Interrupt Enable Falling Edge register (address R = 10h to 12h 10h 11h 12h) bit description …continued Bit Symbol Description 2 SESS_VALID_F Session Valid Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on SESS_VLD. 1 VBUS_VALID_F V BUS A_VBUS_VLD. 0 HOST_DISCON_F Host Disconnect Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on HOST_DISCON ...
Page 55
... NXP Semiconductors Table 38. USB Interrupt Latch register (address R = 14h) bit description Bit Symbol Description reserved 4 ID_GND_L ID Ground Latch: Automatically set when an unmasked event occurs on ID_GND. Cleared when this register is read. 3 SESS_END_L Session End Latch: Automatically set when an unmasked event occurs on SESS_END. ...
Page 56
... NXP Semiconductors 10.1.13 Vendor-specific registers Addresses 30h to 3Fh contain vendor-specific registers. 10.1.14 Power Control register This register controls various aspects of the ISP1504. the register. Table 42. Power Control register (address R = 3Dh to 3Fh 3Dh 3Eh 3Fh) bit allocation Bit 7 Symbol Reset ...
Page 57
... NXP Semiconductors 11. ElectroStatic Discharge (ESD) 11.1 ESD protection The pins that are connected to the USB connector (DP, DM, ID, V minimum ESD protection. Capacitors 0.1 F and 1 F must be connected in parallel from V Remark: Capacitors 0.1 F and 1 F are also required by Universal Serial Bus Specification Rev. 2.0 . For details on the requirements for C ...
Page 58
... NXP Semiconductors 12. Limiting values Table 44. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage CC V input/output supply voltage CC(I/O) V input voltage I V electrostatic discharge ESD voltage I latch-up current lu T storage temperature stg The ISP1504 has been tested according to the additional requirements listed in Universal Serial Bus Specification Rev. 2.0, [1] Section 7 ...
Page 59
... NXP Semiconductors 14. Static characteristics Table 46. Static characteristics: supply pins CC(I/O) Typical values are 3 Symbol Parameter V voltage on pin REG3V3 (REG3V3) V voltage on pin REG1V8 (REG1V8) V power-on reset trip voltage POR(trip) I supply current CC I supply current on CC(I/O) pin V CC(I/O) [1] A continuous stream packets with minimum inter-packet gap and all data bits set to logic 0 for continuous toggling. ...
Page 60
... NXP Semiconductors Table 47. Static characteristics: digital pins Digital pins: CLOCK, DIR, STP, NXT, DATA[7:0], RESET_N and CHIP_SELECT_N; unless otherwise specifi CC(I/O) Typical values are 3 Symbol Parameter V HIGH-level output voltage HIGH-level output current LOW-level output current OL I off-state output current ...
Page 61
... NXP Semiconductors Table 50. Static characteristics: analog I/O pins (DP CC(I/O) Typical values are 3 Symbol Parameter Original USB transceiver (low-speed and full-speed) Input levels (differential receiver) V differential input sensitivity voltage DI V differential common mode voltage CM range Input levels (single-ended receivers) ...
Page 62
... NXP Semiconductors Table 50. Static characteristics: analog I/O pins (DP CC(I/O) Typical values are 3 Symbol Parameter Resistance R pull-down resistance on pin DP DN(DP) R pull-down resistance on pin DM DN(DM) Termination Z driver output impedance on pin DP O(drv)(DP) Z driver output impedance on pin DM O(drv)(DM) Z input impedance exclusive of ...
Page 63
... NXP Semiconductors Table 53. Static characteristics CC(I/O) Typical values are 3 Symbol Parameter R pull-up resistance on pin V UP(VBUS) R pull-down resistance on DN(VBUS) pin V BUS R idle input resistance on I(idle)(VBUS)(A) pin V (A-device) BUS R idle input resistance on I(idle)(VBUS)(B) pin V (B-device) BUS Table 54. Static characteristics: ID detection circuit 3.6 V ...
Page 64
... NXP Semiconductors 120 I CC(cp) (mA) 100 = denotes charge pump supply current. CC(cp) Fig 25. Charge pump supply current as a function of V output current BUS 5. O(VBUS O(VBUS (V) 5.00 4.50 4.00 3 3.1 3.2 3.3 V denotes charge pump supply voltage. CC(cp) Fig 27. V output voltage as a function of charge ...
Page 65
... Conditions 4 capacitor each on pins REG1V8 and REG3V3 ISP1504ABS ISP1504CBS ISP1504ABS ISP1504CBS applicable only when clock is applied on pin XTAL1 only for square wave input only for square wave input only for square wave input measured from power good or assertion of pin STP Rev. 03 — ...
Page 66
... NXP Semiconductors Table 57. Dynamic characteristics: digital I/O pins +85 C; unless otherwise specified. CC amb Symbol Parameter 1.95 V CC(I/O) t DATA set-up time with respect to su(DATA) the rising edge of pin CLOCK t DATA hold time with respect to h(DATA) the rising edge of pin CLOCK ...
Page 67
... NXP Semiconductors Table 58. Dynamic characteristics: analog I/O pins (DP and CC(I/O) Symbol Parameter V output signal crossover CRS voltage Low-speed driver t transition time: rise time LR t transition time: fall time LF t rise and fall time matching t LRFM Driver timing t driver propagation delay ...
Page 68
... NXP Semiconductors HSR Fig 29. Rise time and fall time 1.8 V logic 0.9 V input PZH t PZL V OH differential V CRS data lines V OL Fig 31. Timing of TX_ENABLE to DP and DM 15.1 ULPI timing ULPI interface timing requirements are given in synchronous mode only. All timing is measured with respect to the ISP1504 CLOCK pin. ...
Page 69
... NXP Semiconductors 16. Application information Table 59. Recommended bill of materials [1] Designator Application C highly recommended for all bypass applications C charge pump is used cp(C_A)-(C_B) C highly recommended for all filter applications C mandatory for peripherals VBUS mandatory for host mandatory for OTG D recommended for all ESD ...
Page 70
... RECEPTACLE GND IP4359CX4/LF SHIELD ESD SHIELD 7 8 SHIELD 9 SHIELD C VBUS C bypass (1) Frequency is version dependent: ISP1504ABS: 19.2 MHz; ISP1504CBS: 26 MHz. Fig 34. Using the ISP1504 with an OTG controller; internal charge pump is utilized and crystal is attached V CC(I/O) DATA0 DATA1 DATA2 CC(I/ RREF V RREF CC(I/O) ...
Page 71
... C VBUS SHIELD 5 SHIELD IP4359CX4/ ESD f i(XTAL1) (1) Frequency is version dependent: ISP1504ABS: 19.2 MHz; ISP1504CBS: 26 MHz. Fig 35. Using the ISP1504 with a standard USB host controller; external 5 V source with built-in FAULT and external square wave input on XTAL1 V V CC(I/ bypass DATA1 DATA0 DATA2 ...
Page 72
... BUS USB STANDARD-B GND RECEPTACLE SHIELD IP4359CX4/ SHIELD 6 D ESD C bypass (1) Frequency is version dependent: ISP1504ABS: 19.2 MHz; ISP1504CBS: 26 MHz. Fig 36. Using the ISP1504 with a standard USB peripheral controller; external crystal V V CC(I/O) CC DATA1 DATA0 1 32 DATA2 V CC(I/ RREF RREF 3 30 CHIP_SELECT_N ...
Page 73
... NXP Semiconductors 17. Package outline HVQFN32: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 0.85 mm terminal 1 index area terminal 1 index area 32 DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
Page 74
... NXP Semiconductors 18. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 18.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
Page 75
... NXP Semiconductors 18.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
Page 76
... NXP Semiconductors Fig 38. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 19. Abbreviations Table 62. Acronym ASIC ATX CD-RW EOP ESD ESR FS HBM HNP HS ID IEC LS NRZI ...
Page 77
... NXP Semiconductors Table 62. Acronym POR RXCMD SE0 SOF SRP SYNC TTL TXCMD USB USB-IF ULPI UTMI UTMI+ 20. References [1] Universal Serial Bus Specification Rev. 2.0 [2] On-The-Go Supplement to the USB 2.0 Specification Rev. 1.3 [3] UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 [4] UTMI+ Specifi ...
Page 78
... NXP Semiconductors 21. Revision history Table 63. Revision history Document ID Release date ISP1504A_ISP1504C_3 20080407 • Modifications: • • • • • • • ISP1504A_ISP1504C_2 20070925 • Modifications: • • • • • • • • ISP1504A_ISP1504C_1 20061019 ISP1504A_ISP1504C_3 Product data sheet ...
Page 79
... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
Page 80
... NXP Semiconductors 24. Tables Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .3 Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5 Table 3. Recommended charge pump capacitor value .12 Table 4. ULPI signal description . . . . . . . . . . . . . . . . . .15 Table 5. Signal mapping during low-power mode . . . . .16 Table 6. Signal mapping for 6-pin serial mode . . . . . . .17 Table 7. Signal mapping for 3-pin serial mode . . . . . . .18 Table 8. Operating states and their corresponding resistor settings ...
Page 81
... NXP Semiconductors 25. Figures Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Fig 2. Pin configuration HVQFN32; top view . . . . . . . . . .5 Fig 3. External capacitors connection . . . . . . . . . . . . . .10 Fig 4. Charge pump capacitor . . . . . . . . . . . . . . . . . . . .12 Fig 5. Internal power-on reset timing . . . . . . . . . . . . . . .20 Fig 6. Power-up and reset sequence required before the ULPI bus is ready for use .22 Fig 7. Interface behavior with respect to RESET_N .23 Fig 8 ...
Page 82
... NXP Semiconductors 26. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Functional description . . . . . . . . . . . . . . . . . . . 7 7.1 ULPI interface controller . . . . . . . . . . . . . . . . . . 7 7.2 USB data serializer and deserializer 7.3 Hi-Speed USB (USB 2.0) ATX . . . . . . . . . . . . . 7 7 ...
Page 83
... NXP Semiconductors 9.15 Avoiding contention on the ULPI data bus . . . 46 10 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.1 Immediate register set . . . . . . . . . . . . . . . . . . 48 10.1.1 Vendor ID and Product ID registers . . . . . . . . 48 10.1.1.1 Vendor ID Low register . . . . . . . . . . . . . . . . . . 48 10.1.1.2 Vendor ID High register . . . . . . . . . . . . . . . . . 48 10.1.1.3 Product ID Low register . . . . . . . . . . . . . . . . . 48 10.1.1.4 Product ID High register . . . . . . . . . . . . . . . . . 48 10.1.2 Function Control register . . . . . . . . . . . . . . . . 48 10 ...