ISP1508AET NXP Semiconductors, ISP1508AET Datasheet
ISP1508AET
Specifications of ISP1508AET
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ISP1508AET Summary of contents
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ISP1508A; ISP1508B ULPI Hi-Speed Universal Serial Bus transceiver Rev. 01 — 14 August 2007 1. General description The ISP1508 is a UTMI+ Low Pin Interface (ULPI) Universal Serial Bus (USB) transceiver that is fully compliant with Universal Serial Bus Specification ...
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... NXP Semiconductors I Complete USB OTG physical front-end that supports Host Negotiation Protocol (HNP) and Session Request Protocol (SRP) N Supports external charge pump or external V N Complete control over USB termination resistors N Data line and V N Integrated V N Integrated cable (ID) detector I Flexible system integration and very low power consumption, optimized for portable ...
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... I Video camera 4. Ordering information Table 1. Ordering information Part Type number Marking CHIP_SEL polarity [1] ISP1508AET 508A active HIGH [1] ISP1508BET 508B active LOW [1] The package marking is the first line of text on the IC package and can be used for IC identification. ISP1508A_ISP1508B_1 Product data sheet ISP1508A; ISP1508B ...
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... NXP Semiconductors 5. Block diagram A4 CLOCK C6, B6, A6, A5, A3, A2, 8 A1, B1 DATA [7:0] ULPI E5 DIR INTERFACE D6 STP D5 NXT C3 CHIP_SEL E1 CFG0 B4 CFG1 B3 CFG2 GLOBAL CLOCKS F5 XTAL1 F6 XTAL2 B2 CC(I/O) E6 REG1V8 E3 REG3V3 Fig 1. Block diagram ISP1508A_ISP1508B_1 Product data sheet ISP1508A; ISP1508B USB DATA ULPI SERIALIZER INTERFACE ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. Pin configuration 6.2 Pin description Table 2. Pin description [1] [2] Symbol Pin Type DATA1 A1 I/O DATA2 A2 I/O DATA3 A3 I/O CLOCK A4 O DATA4 A5 I/O DATA5 A6 I/O DATA0 B1 I CC(I/O) CFG2 B3 I CFG1 B4 I DATA6 ...
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... NXP Semiconductors Table 2. Pin description …continued [1] [2] Symbol Pin Type DM C1 AI/O RREF C2 AI/O CHIP_SEL C3 I TEST_N C4 I DATA7 PSW_N D4 OD NXT D5 O STP D6 I CFG0 E1 I FAULT E2 I REG3V3 E3 P GND C5, D2 DIR E5 O REG1V8 E6 P n.c. F1 ISP1508A_ISP1508B_1 Product data sheet ...
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... NXP Semiconductors Table 2. Pin description …continued [1] [2] Symbol Pin Type AI/O BUS XTAL1 F5 AI/O XTAL2 F6 AI/O [1] Symbol names ending with underscore N (for example, NAME_N) indicate active LOW signals. [ input output; I/O = digital input/output open-drain output; AI/O = analog input/output power or ground pin. ...
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... NXP Semiconductors 7.3 RREF Resistor reference analog I/O pin RREF pin and GND. This provides an accurate voltage reference that biases internal analog circuitry. Less accurate resistors cannot be used. It will affect the biasing current for analog circuits, thus the USB signal quality. ...
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... NXP Semiconductors 7.7 ID For OTG applications, the ID (identification) pin is connected to the ID pin of the micro-AB receptacle. As defined in On-The-Go Supplement to the USB 2.0 Specification Rev. 1.2 , the ID pin dictates the initial role of the link detected as HIGH, the link must assume the role of a peripheral detected as LOW, the link must assume a host role ...
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... NXP Semiconductors Fig 3. V 7.10 REG3V3 and REG1V8 These are output voltage pins from the internal regulator. These supplies are used internally to power digital and analog circuits. For proper operation of the regulator, REG3V3 and REG1V8 must each be connected to a 0.1 F capacitor in parallel with a 4.7 F low ESR capacitor. ...
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... NXP Semiconductors Table 5. CFG1 When a clock is driven into XTAL1, XTAL2 must be left open crystal is attached, it requires a capacitor on each terminal of the crystal to GND. The recommended crystal specification and required external capacitors are given in and Table Table 6. External capacitor values for 13 MHz or 19.2 MHz clock frequency ...
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... NXP Semiconductors 7.14 STP ULPI stop input pin. Synchronous to the rising edge of CLOCK. The link must assert STP to signal the end of a USB transmit packet or a register write operation. When DIR is asserted, the link can optionally assert STP for one cycle to abort the ISP1508, causing it to de-assert DIR in the next clock cycle ...
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... NXP Semiconductors 8. Functional description 8.1 ULPI interface controller The ISP1508 provides an 8-pin or 12-pin interface that is compliant with UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 . This interface must be connected to a USB link. The ULPI interface controller provides the following functions: • ...
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... NXP Semiconductors • High-speed disconnect detector • 45 • 1.5 k pull-up resistor on DP • bus terminations on DP and DM For details on controlling resistor settings, see 8.4 Voltage regulator The ISP1508 contains a built-in voltage regulator that conditions the V inside the ISP1508. The voltage regulator: • ...
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... NXP Semiconductors • From DP (2.7 V level) to DATA1 (V 8.7 OTG module This module contains several sub-blocks that provide all the functionality required by the USB OTG specification. Specifically, it provides the following circuits: • ID detector to sense the ID pin of the micro-USB cable. The ID pin dictates which device is initially confi ...
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... NXP Semiconductors 8.7.3 SRP charge and discharge resistors The ISP1508 provides on-chip resistors for short-term charging and discharging of V These are used by the B-device to request a session, prompting the A-device to restore the V BUS previous session by setting the DISCHRG_VBUS register bit to logic 1 and waiting for SESS_END to be logic 1 ...
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... NXP Semiconductors Fig 5. Internal power-on reset timing 8.11 Power-up, reset and bus idle sequence Figure 6 On power-up, the ISP1508 performs an internal power-on reset and asserts DIR to indicate to the link that the ULPI bus cannot be used. When the internal PLL is stable, the ISP1508 de-asserts DIR and drives 60 MHz clock out from the CLOCK pin ...
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... NXP Semiconductors CC(I/O) CHIP_SEL REG1V8 t PWRUP Internal POR XTAL1 CLOCK (output) DATA[7:0] DIR STP NXT applied to the ISP1508 turned on. ULPI interface pins CLOCK, DATA[7:0], DIR and NXT are in 3-state as long as CHIP_SEL is CC(I/O) non-active CHIP_SEL turns from non-active to active. The ISP1508 regulator starts to turn on. ULPI pads are not in 3-state and may either drive to LOW or HIGH ...
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... NXP Semiconductors The interface protect feature prevents unwanted activity of the ISP1508 whenever the ULPI interface is not correctly driven by the link. For example, when the link powers up more slowly than the ISP1508. The interface protect feature can be disabled by setting the INTF_PROT_DIS bit to logic 1. ...
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... NXP Semiconductors 9. Modes of operation 9.1 Power modes When both V to all the remaining pins, including V the ISP1508 chip. When both V ISP1508 will be fully functional as in normal mode. When V ISP1508, the application system must detect the low voltage condition and set the CHIP_SEL pin to non-active state to put the ISP1508 in power-down mode ...
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... NXP Semiconductors using pull-up or pull-down resistors to avoid floating input condition. Other pins (see Section detect the CHIP_SEL pin status. 9.2 ULPI modes The ISP1508 ULPI interface can be programmed to operate in five modes. In each mode, the signals on the data bus are reconfigured as described in the following subsections. ...
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... NXP Semiconductors Table 9. ULPI signal description Signal name Direction on Signal description the ISP1508 DIR O Direction: Controls the direction of data bus DATA[7:0]. In synchronous mode, the ISP1508 drives DIR to LOW by default, making the data bus an input so that the ISP1508 can listen for TXCMD from the link. The ISP1508 drives DIR to HIGH only when it has data for the link ...
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... NXP Semiconductors 9.2.3 6-pin full-speed or low-speed serial mode If the link requires a 6-pin serial interface to transmit and receive full-speed or low-speed USB data, it can set the ISP1508 to 6-pin serial mode. In 6-pin serial mode, the data bus definition changes to that shown in 6PIN_FSLS_SERIAL bit in the Interface Control register to logic 1. To exit 6-pin serial mode, the link asserts the STP signal ...
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... NXP Semiconductors Table 12. Signal mapping for 3-pin serial mode Signal Maps to SE0 DATA2 INT DATA3 Reserved DATA[7:4] 9.2.5 Transparent UART mode In transparent UART mode, the ISP1508 functions as a voltage level shifter between the following pins: • From pin DATA0 (V • From pin DP (2.7 V level) to pin DATA1 (V The USB transceiver is used to drive the UART transmitting signal on the DM line ...
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... NXP Semiconductors After the register configuration is complete weak pull-up resistor will be enabled on the DP and DATA0 pins. This is to avoid the possible floating condition on these input pins when UART mode is enabled. 2. The 39 3. One clock cycle after DIR goes from LOW to HIGH, the ISP1508 will drive the data bus for fi ...
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... NXP Semiconductors (1) CLOCK (2) CLOCK DATA[7:0] DIR STP NXT UART mode (1) Clock remains powered when the CLOCK_SUSPENDM register bit is logic 1. (2) Clock is powered down when the CLOCK_SUSPENDM register bit is logic 0 (default). Fig 8. Interface behavior when entering UART mode CLOCK CLOCK DATA[7:0] (1) Clock remains powered when the CLOCK_SUSPENDM register bit is logic 1. ...
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... NXP Semiconductors 9.3 USB state transitions A Hi-Speed USB peripheral, host or OTG device handles more than one electrical state as defined in Universal Serial Bus Specification Rev. 2.0 and On-The-Go Supplement to the USB 2.0 Specification Rev. 1.2 . The ISP1508 accommodates various states through register settings of the XCVRSELECT[1:0], TERMSELECT, OPMODE[1:0], DP_PULLDOWN and DM_PULLDOWN bits ...
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... NXP Semiconductors Table 14. Operating states and their corresponding resistor settings Signaling mode Register settings XCVR SELECT [1:0] Peripheral 01b high-speed or full-speed suspend Peripheral 01b high-speed or full-speed resume Peripheral Test J or 00b Test K OTG settings OTG device 00b peripheral chirp OTG device ...
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... NXP Semiconductors 10. Protocol description 10.1 ULPI references The ISP1508 provides an 8-pin or 12-pin ULPI interface to communicate with the link highly recommended that users of the ISP1508 read UTMI+ Specification Rev. 1.0 and UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 . 10.2 TXCMD and RXCMD Commands between the ISP1508 and the link are described in the following subsections ...
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... NXP Semiconductors The ISP1508 will automatically send an RXCMD whenever there is a change in any of the RXCMD data fields. The link must be able to accept an RXCMD at any time; including single RXCMDs, back-to-back RXCMDs, and RXCMDs at any time during USB receive packets when NXT is LOW. An example is shown in refer to UTMI+ Low Pin Interface (ULPI) Specifi ...
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... NXP Semiconductors Table 17. LINESTATE[1:0] encoding for upstream facing ports: peripheral [1] DP_PULLDOWN = 0. Mode LINESTATE[1: [1] !squelch indicates inactive squelch. !HS_Differential_Receiver_Output indicates inactive HS_Differential_Receiver_Output. Table 18. LINESTATE[1:0] encoding for downstream facing ports: host DP_PULLDOWN and DM_PULLDOWN = 1. Mode Low-speed XCVRSELECT[1:0] 10 TERMSELECT 1 OPMODE[1:0] X LINESTATE[1:0] 00 SE0 01 LS-K 10 LS-J ...
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... NXP Semiconductors USE_EXT_VBUS_IND, IND_PASSTHRU Fig 11. RXCMD A_VBUS_VLD indicator source 10.2.2.3 Using and selecting the V The V BUS link whenever there is a change in the V must first enable the corresponding interrupts in the USB Interrupt Enable Rising and USB Interrupt Enable Falling registers. The link can use the V shows the recommended usage for typical applications ...
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... NXP Semiconductors OTG devices: provide a minimum there is no need for an overcurrent detection circuit because the internal A_VBUS_VLD comparator is sufficient. If the OTG A-device provides more than 100 overcurrent detector must be used and The OTG A-device also uses SESS_VLD to detect when an OTG A-device is initiating V pulsing SRP ...
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... NXP Semiconductors 10.3 Register read and write operations Figure 12 addressing and extended addressing register operations. Extended register addressing is optional for links. Note that register operations will be aborted if the ISP1508 asserts DIR during the operation. When a register operation is aborted, the link must retry until successful. For more information on register operations, refer to UTMI+ Low Pin Interface (ULPI) Specifi ...
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... NXP Semiconductors than 7 ms after reset time T up its clock within 5.6 ms, leaving 200 s for the link to start transmitting the Chirp K, and 1.2 ms for the Chirp K to complete (worst case with 10 % slow clock). b. Host chirp: If the host does not detect the peripheral chirp, it must continue asserting SE0 until the end of reset ...
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... NXP Semiconductors USB reset T 0 TXCMD (REGW) SE0 DATA [ 7:0 ] DIR STP NXT 01 (FS) XCVR SELECT TERM SELECT 00 (normal) OP MODE J (01b) SE0 (00b) LINE STATE TXCMD SE0 (REGW) DATA [ 7:0 ] DIR STP NXT 01 (FS) XCVR SELECT TERM SELECT 00 (normal) OP MODE J (01b) ...
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... NXP Semiconductors 10.5 USB packet transmit and receive An example of a packet transmit and receive is shown in packets, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 . link sends TXCMD CLOCK TXCMD DATA[7:0] DIR STP NXT Fig 14. Example of using the ISP1508 to transmit and receive USB data 10 ...
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... NXP Semiconductors Table 23. Link decision times Packet sequence High-speed link delay Transmit-Transmit (host only) Receive-Transmit (host or peripheral) Receive-Receive 1 (peripheral only) Transmit-Receive 92 (host or peripheral DATA DM CLOCK DATA [7:0] DIR STP NXT TX end delay (two to five clocks) Fig 15. High-speed transmit-to-transmit packet timing ISP1508A_ISP1508B_1 ...
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... NXP Semiconductors DP or DATA EOP DM CLOCK DATA [7: DIR STP NXT RX end delay (three to eight clocks) Fig 16. High-speed receive-to-transmit packet timing 10.6 Preamble Preamble packets are headers to low-speed packets that must travel over a full-speed bus, between a host and a hub. To enter preamble mode, the link sets XCVRSELECT[1:0] = 11b in the Function Control register ...
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... NXP Semiconductors CLOCK DATA[7: Fig 17. Preamble sequence 10.7 USB suspend and resume 10.7.1 Full-speed or low-speed host-initiated suspend and resume Figure 18 suspend and sometime later initiates resume signaling to wake-up the downstream peripheral. Note that LINESTATE updates. The sequence of events for a host and a peripheral, both with ISP1508 follows: 1 ...
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... NXP Semiconductors idle DATA [ 7:0 ] DIR STP NXT OPMODE 00b LINE J STATE CLOCK TXCMD (REGW) DATA [ 7:0 ] DIR STP NXT OPMODE SUSPEND M LINE STATE DP DM Timing is not to scale. Fig 18. Full-speed suspend and resume 10.7.2 High-speed suspend and resume Figure 19 suspend and then initiates resume signaling. The high-speed peripheral will wake up and return to high-speed operations ...
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... NXP Semiconductors The sequence of events related to a host and a peripheral, both with ISP1508 follows. 1. High-speed idle: Initially, the host and the peripheral are idle. The host has its 15 k pull-down resistors enabled (DP_PULLDOWN and DM_PULLDOWN are set to 1b) and Full-speed suspend: When the peripheral sees no bus activity for 3 ms, it enters the suspend state ...
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... NXP Semiconductors HS idle TXCMD (REGW) DATA [ 7:0 ] DIR STP NXT XCVR 00b SELECT TERM SELECT OP MODE !SQUELCH SQUELCH (00b) (01b) LINE STATE CLOCK TXCMD (REGW) DATA [ 7:0 ] DIR STP NXT XCVR 00b SELECT TERM SELECT OP MODE SUSPEND M !SQUELCH SQUELCH (01b) (00b) ...
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... NXP Semiconductors 10.7.3 Remote wake-up The ISP1508 supports peripherals that initiate remote wake-up resume. When placed into USB suspend, the peripheral link remembers at what speed it was originally operating. Depending on the original speed, the link follows one of the protocols detailed here. In Figure 20, timing is not to scale, and not all RXCMD LINESTATE updates are shown ...
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... NXP Semiconductors LINESTATE DATA [ 7:0 ] DIR STP NXT XCVR SELECT TERM SELECT OP MODE TXCMD LINESTATE REGW DATA [ 7:0 ] DIR STP NXT XCVR SELECT TERM SELECT OP MODE Timing is not to scale. Fig 20. Remote wake-up from low-power mode 10.8 No automatic SYNC and EOP generation (optional) This setting allows the link to turn off the automatic SYNC and EOP generation, and must be used for high-speed packets only ...
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... NXP Semiconductors PHY will not transmit any EOP. The ISP1508 will also detect if the PID byte is A5h, indicating an SOF packet, and automatically send a long EOP when STP is asserted. To transmit chirp and resume signaling, the link must set OPMODE to 10b. CLOCK DATA ...
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... NXP Semiconductors 10.9.1 OTG comparators The ISP1508 provides comparators that conform to On-The-Go Supplement to the USB 2.0 Specification Rev. 1.2 requirements of V and V B_SESS_END V A_SESS_VLD are communicated to the link by RXCMDs as described in comparators is described in 10.9.2 Pull-up and pull-down resistors The USB resistors on DP and DM can be used to initiate data-line pulsing SRP. The link must set the required bus state using the mode settings in 10 ...
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... NXP Semiconductors SYNC DATA0 (TX_ENABLE) DATA1 (TX_DAT) DATA2 (TX_SE0) DATA4 (RX_DP) DATA5 (RX_DM) DATA6 (RX_RCV Fig 22. Example of transmit followed by receive in 6-pin serial mode SYNC DATA0 (TX_ENABLE) DATA1 (TX_DAT/ RX_RCV) DATA2 (TX_SE0/ RX_SE0 Fig 23. Example of transmit followed by receive in 3-pin serial mode ISP1508A_ISP1508B_1 Product data sheet ISP1508A ...
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... NXP Semiconductors 10.11 Aborting transfers The ISP1508 supports aborting transfers on the ULPI bus. For details, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1, Section 3.8.4. 10.12 Avoiding contention on the ULPI data bus Because the ULPI data bus is bidirectional, avoid situations in which both the link and the PHY simultaneously drive the data bus ...
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... NXP Semiconductors 11. Register map Table 24. Register map Field name Size (bits) Vendor ID Low 8 Vendor ID High 8 Product ID Low 8 Product ID High 8 Function Control 8 Interface Control 8 OTG Control 8 USB Interrupt Enable Rising 8 USB Interrupt Enable Falling 8 USB Interrupt Status 8 USB Interrupt Latch 8 Debug 8 Scratch ...
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... NXP Semiconductors 11.1.3 Product ID Low register The bit description of the Product ID Low register is given in Table 27. Product ID Low register (address R = 02h) bit description Legend: * reset value Bit Symbol Access PRODUCT_ID_ R LOW[7:0] 11.1.4 Product ID High register The bit description of the register is given in Table 28. ...
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... NXP Semiconductors Table 30. Function Control register (address R = 04h to 06h 04h 05h 06h) bit description Bit Symbol Description OPMODE[1:0] Operation Mode: Selects the required bit-encoding style during transmit. 00b — Normal operation 01b — Non-driving 10b — Disable bit-stuffing and NRZI encoding 11b — ...
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... NXP Semiconductors Table 32. Interface Control register (address R = 07h to 09h 07h 08h 09h) bit description Bit Symbol 7 INTF_PROT_DIS 6 IND_PASSTHRU 5 IND_COMPL CLOCK_SUSPENDM 2 CARKIT_MODE 1 3PIN_FSLS_SERIAL 0 6PIN_FSLS_SERIAL 11.4 OTG Control register This register controls various OTG functions of the ISP1508. The bit allocation of the OTG Control register is given in ...
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... NXP Semiconductors Table 33. OTG Control register (address R = 0Ah to 0Ch 0Ah 0Bh 0Ch) bit allocation Bit 7 Symbol USE_EXT_ DRV_ VBUS_IND VBUS_EXT Reset 0 Access R/W/S/C R/W/S/C Table 34. OTG Control register (address R = 0Ah to 0Ch 0Ah 0Bh 0Ch) bit description Bit Symbol Description 7 USE_EXT_ Use External V VBUS_IND 0b — ...
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... NXP Semiconductors Table 35. USB Interrupt Enable Rising register (address R = 0Dh to 0Fh 0Dh 0Eh 0Fh) bit allocation Bit 7 Symbol reserved Reset 0 Access R/W/S/C R/W/S/C Table 36. USB Interrupt Enable Rising register (address R = 0Dh to 0Fh 0Dh 0Eh 0Fh) bit description Bit Symbol Description reserved ...
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... NXP Semiconductors 11.7 USB Interrupt Status register This register (see Table 39. USB Interrupt Status register (address R = 13h) bit allocation Bit 7 Symbol reserved Reset X Access R Table 40. USB Interrupt Status register (address R = 13h) bit description Bit Symbol ID_GND 3 SESS_END 2 SESS_VALID 1 VBUS_VALID 0 HOST_DISCON 11.8 USB Interrupt Latch register The bits of the USB Interrupt Latch register are automatically set by the ISP1508 when an unmasked change occurs on the corresponding interrupt source signal ...
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... NXP Semiconductors Table 42. USB Interrupt Latch register (address R = 14h) bit description Bit Symbol ID_GND_L 3 SESS_END_L 2 SESS_VALID_L 1 VBUS_VALID_L 0 HOST_DISCON_L 11.9 Debug register The bit allocation of the Debug register is given in current value of signals useful for debugging. Table 43. Debug register (address R = 15h) bit allocation ...
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... NXP Semiconductors For bit allocation, see Table 46. Carkit Control register (address R = 19h to 1Bh 19h 1Ah 1Bh) bit allocation Bit 7 Symbol Reset 0 Access R/W/S/C R/W/S/C Table 47. Carkit Control register (address R = 19h to 1Bh 19h 1Ah 1Bh) bit description Bit Symbol Description reserved; the link must never write logic 1 to these bits ...
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... NXP Semiconductors 12. Limiting values Table 50. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage CC V input/output supply voltage CC(I/O) V input voltage I V electrostatic discharge ESD voltage I latch-up current lu T storage temperature stg [1] The ISP1508 has been tested according to the additional requirements listed in Universal Serial Bus Specification Rev. 2.0, Section 7 ...
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... NXP Semiconductors 14. Static characteristics Table 52. Static characteristics: supply pins CC(I/O) Typical case refers 3 Symbol Parameter V power-on reset trip voltage POR(trip) I supply current CC I static supply current on CC(I/O)(stat) pin V CC(I/O) I supply current on CC(I/O) pin V CC(I/O) [1] The actual value of I varies depending on the capacitance loading, interface voltage and bus activity. Use the value provided here CC(I/O) only for reference ...
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... NXP Semiconductors Table 53. Static characteristics: digital pins (CLOCK, DIR, STP, NXT, DATA[7:0], CHIP_SEL, CFG2, CFG1, TEST_N) …continued CC(I/O) Symbol Parameter Impedance Z load impedance L Pull-up and pull-down I pull-down current pd I pull-up current pu Capacitance C input capacitance in Table 54. Static characteristics: digital pin FAULT 4.5 V ...
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... NXP Semiconductors Table 56. Static characteristics: analog pins (DP CC(I/O) Typical case refers 3 Symbol Parameter V differential common mode CM voltage range Input levels (single-ended receivers) V LOW-level input voltage IL V HIGH-level input voltage IH Output levels V LOW-level output voltage OL V HIGH-level output voltage ...
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... NXP Semiconductors Table 56. Static characteristics: analog pins (DP CC(I/O) Typical case refers 3 Symbol Parameter Leakage current I off-state leakage current LZ Capacitance C input capacitance in Resistance R pull-down resistance on DN(DP) pin DP R pull-down resistance on DN(DM) pin DM Termination Z driver output impedance on O(drv)(DP) pin DP Z driver output impedance on ...
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... NXP Semiconductors Table 58. Static characteristics: ID detection circuit CC(I/O) Typical case refers 3 Symbol Parameter t ID detection time detector threshold th(ID) voltage R ID pull-up resistance UP(ID) R weak pull-up resistance weakPU(ID) on pin ID V pull-up voltage on pin ID PU(ID) Table 59. Static characteristics: resistor reference 4.5 V ...
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... NXP Semiconductors 15. Dynamic characteristics Table 62. Dynamic characteristics: reset and power CC(I/O) Typical case refers 3 Symbol Parameter t internal power-on reset pulse W(POR) width t REG1V8 HIGH pulse width w(REG1V8_H) t REG1V8 LOW pulse width w(REG1V8_L) t PLL startup time startup(PLL) t oscillator clock detector delay ...
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... NXP Semiconductors Table 64. Dynamic characteristics: CLOCK output CC(I/O) Typical case refers 3 Symbol Parameter f output frequency on o(CLOCK) pin CLOCK t RMS output jitter on jit(o)(CLOCK)RMS pin CLOCK output clock duty cycle on o(CLOCK) pin CLOCK Table 65. Dynamic characteristics: digital I/O pins (SDR 3 4.5 V ...
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... NXP Semiconductors Table 66. Dynamic characteristics: digital I/O pins (DDR CC(I/O) Typical case refers 3 Symbol Parameter Conditions t output delay output delay with respect to the positive edge of CLOCK; d(o) time output-only pins (DIR, NXT) output delay with respect to the positive and negative edges of CLOCK ...
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... NXP Semiconductors Table 68. Dynamic characteristics: analog I/O pins (DP, DM) in transparent UART mode CC(I/O) Typical case refers 3 Symbol Parameter Low-speed driver characteristics (DM only) t rise time for UART TXD r(UART) t fall time for UART TXD f(UART) t driver propagation delay PLH(drv) (LOW to HIGH) ...
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... NXP Semiconductors Table 69. Dynamic characteristics: analog I/O pins (DP, DM) in serial mode CC(I/O) Typical case refers 3 Symbol Parameter Single-ended receiver t single-ended propagation delay PLH(se) (LOW to HIGH) t single-ended propagation delay PHL(se) (HIGH to LOW HSR Fig 24. Rise time and fall time 1.8 V logic 0 ...
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... NXP Semiconductors CLOCK Control IN DATA IN Control OUT (DIR, NXT) DATA OUT Fig 28. ULPI timing interface ISP1508A_ISP1508B_1 Product data sheet (STP (8-bit) (8-bit) Rev. 01 — 14 August 2007 ISP1508A; ISP1508B ULPI HS USB transceiver t d(o) t d(o) t d(o) © NXP B.V. 2007. All rights reserved. ...
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... NXP Semiconductors 16. Application information Table 70. Recommended bill of materials Designator Application R mandatory in all applications RREF R recommended for peripherals S(VBUS) or external 5 V applications C in all applications XTAL C mandatory for peripherals VBUS mandatory for host mandatory for OTG C highly recommended for all bypass applications ...
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R S(VBUS BUS USB STANDARD-B RECEPTACLE 4 GND C VBUS 5 SHIELD 6 SHIELD (1) Connect to either GND depending on the clock frequency used. See CC(I/O) Fig 29. ISP1508 in ...
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V IN FAULT V BUS R pullup SWITCH ON OUT 1 V BUS USB ID MICRO-AB RECEPTACLE 5 GND C VBUS 6 SHIELD IP4359CX4/LF 7 SHIELD 8 SHIELD 9 SHIELD C bypass (1) Connect ...
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V IN FAULT V BUS R pullup SWITCH ON OUT V 1 BUS USB STANDARD-A RECEPTACLE GND 4 C VBUS SHIELD 5 SHIELD 6 C bypass (1) Connect to either GND depending ...
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... NXP Semiconductors 17. Package outline TFBGA36: plastic thin fine-pitch ball grid array package; 36 balls; body 3.5 x 3.5 x 0.8 mm ball A1 index area 1 ball A1 1 index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.25 0.90 0.35 mm 1.15 0.15 0.75 0.25 OUTLINE VERSION IEC ...
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... NXP Semiconductors 18. Soldering This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 18.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 18.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 33. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 19. Abbreviations Table 73. Acronym ASIC ATX CDM CD-RW DDR EMI EOP ESD ESR FPGA FS HBM ...
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... NXP Semiconductors Table 73. Acronym OTG PDA PHY PID PLL POR RXCMD RXD SDR SE0 SOC SOF SRP SYNC TTL TXCMD TXD UART ULPI USB USB-IF UTMI UTMI+ WLCSP 20. Glossary A-device — An OTG device with an attached micro-A plug B-device — An OTG device with an attached micro-B plug Link — ...
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... NXP Semiconductors [6] USB 2.0 Transceiver Macrocell Interface (UTMI) Specification Ver. 1.05 [7] Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM) (JESD22-A114D) [8] Electrostatic Discharge (ESD) Sensitivity Testing Machine Model (MM) (JESD22-A115-A) [9] Field-Induced Charged-Device Model Test Method for Electrostatic Discharge-Withstand Thresholds of Microelectronic Components (JESD22-C101-A) 22 ...
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... For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail ...
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... NXP Semiconductors 25. Tables Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .3 Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5 Table 3. OTG Control register power control bits . . . . . .8 Table 4. Recommended V capacitor value . . . . . . . .9 BUS Table 5. Allowed crystal or clock frequency on the XTAL1 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Table 6. External capacitor values for 13 MHz or 19.2 MHz clock frequency . . . . . . . . . . . . . . . .11 Table 7. External capacitor values for 24 MHz or 26 MHz clock frequency ...
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... NXP Semiconductors Table 51. Recommended operating conditions . . . . . . . .59 Table 52. Static characteristics: supply pins . . . . . . . . . .60 Table 53. Static characteristics: digital pins (CLOCK, DIR, STP, NXT, DATA[7:0], CHIP_SEL, CFG2, CFG1, TEST_N .60 Table 54. Static characteristics: digital pin FAULT . . . . . .61 Table 55. Static characteristics: digital pin PSW_N . . . . .61 Table 56. Static characteristics: analog pins (DP, DM) . .61 Table 57 ...
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... NXP Semiconductors 26. Figures Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Fig 2. Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . .5 Fig 3. V pin internal pull-up and pull-down scheme .10 BUS Fig 4. Digital overcurrent detection scheme .16 Fig 5. Internal power-on reset timing . . . . . . . . . . . . . . .17 Fig 6. Power-up and reset sequence required before the ULPI bus is ready for use .18 Fig 7 ...
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... NXP Semiconductors 27. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Detailed description of pins . . . . . . . . . . . . . . . 7 7.1 DATA[7: 7 CC(I/O) 7.3 RREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7.4 DP and 7.5 FAULT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7.6 PSW_N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BUS 7 ...
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... NXP Semiconductors 11.1.1 Vendor ID Low register . . . . . . . . . . . . . . . . . . 50 11.1.2 Vendor ID High register . . . . . . . . . . . . . . . . . 50 11.1.3 Product ID Low register . . . . . . . . . . . . . . . . . 51 11.1.4 Product ID High register . . . . . . . . . . . . . . . . . 51 11.2 Function Control register . . . . . . . . . . . . . . . . 51 11.3 Interface Control register . . . . . . . . . . . . . . . . 52 11.4 OTG Control register . . . . . . . . . . . . . . . . . . . 53 11.5 USB Interrupt Enable Rising register . . . . . . . 54 11.6 USB Interrupt Enable Falling register . . . . . . . 55 11 ...