ISP1505ABS NXP Semiconductors, ISP1505ABS Datasheet
ISP1505ABS
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ISP1505ABS Summary of contents
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IMPORTANT NOTICE Dear customer from August 2 2008, the wireless operations of NXP have moved to a new company, ST-NXP Wireless result, the following changes are applicable to the attached document. ● Company name - NXP ...
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ISP1505A; ISP1505C ULPI Hi-Speed USB host and peripheral transceiver Rev. 03 — 26 August 2008 1. General description The ISP1505 is a Universal Serial Bus (USB) high-speed host and peripheral transceiver that is fully compliant with Universal Serial Bus Specification ...
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... N 60 MHz, 8-bit interface between the core and the transceiver N Supports 60 MHz output clock configuration N Integrated Phase-Locked Loop (PLL) supporting one crystal or clock frequency: 19.2 MHz (ISP1505ABS) and 26 MHz (ISP1505CBS) N Fully programmable ULPI-compliant register set N Internal Power-On Reset (POR) circuit I ...
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... NXP Semiconductors 4. Ordering information Table 1. Ordering information Part Type number Marking Crystal or clock frequency [1] ISP1505ABS 05A 19.2 MHz [1] ISP1505CBS 05C 26 MHz [1] The package marking is the first line of text on the IC package and can be used for IC identification. ISP1505A_ISP1505C_3 Product data sheet ISP1505A; ISP1505C ...
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... NXP Semiconductors 5. Block diagram 21 CLOCK 15 STP 14 DIR 16 NXT ULPI 1, 2, INTERFACE 17 to 20, 8 22, 24 DATA [7:0] 12 RESET_N/ PSW_N 10 XTAL1 11 XTAL2 CC(I/O) 9 REG3V3 13 REG1V8 Fig 1. Block diagram ISP1505A_ISP1505C_3 Product data sheet ULPI HS USB host and peripheral transceiver USB DATA SERIALIZER ULPI INTERFACE ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. 6.2 Pin description Table 2. Pin description [1][2] Symbol Pin Type DATA1 1 I/O DATA0 2 I CC(I/O) RREF /FAULT 8 AI/O BUS REG3V3 9 P XTAL1 10 AI XTAL2 11 AO ISP1505A_ISP1505C_3 Product data sheet terminal 1 index area ...
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... NXP Semiconductors Table 2. Pin description …continued [1][2] Symbol Pin Type RESET_N/PSW_N 12 I/O REG1V8 13 P DIR 14 O STP 15 I NXT 16 O DATA7 17 I/O DATA6 18 I/O DATA5 19 I/O DATA4 20 I/O CLOCK 21 O DATA3 22 I CC(I/O) DATA2 24 I/O GND die P pad [1] Symbol names ending with underscore N, for example, NAME_N, indicate active LOW signals. ...
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... NXP Semiconductors 7. Functional description 7.1 ULPI interface controller The ISP1505 provides a 12-pin interface that is compliant with UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 . This interface must be connected to the USB link. The ULPI interface controller provides the following functions: • ...
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... NXP Semiconductors • High-speed disconnect detector • 45 • 1.5 k pull-up resistor on DP for full-speed peripheral mode • bus terminations on DP and DM for host and OTG modes For details on controlling resistor settings, see 7.4 Voltage regulator The ISP1505 contains a built-in voltage regulator that conditions the V inside the ISP1505. The voltage regulator: • ...
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... NXP Semiconductors While it is possible for the external 5 V supply to use the ISP1505 internal A_VBUS_VLD comparator, typical 5 V supplies must provide their own power fault indicator that can be connected as an input to the ISP1505 FAULT pin. 7.6.2 Session valid comparator The session valid comparator is a TTL-level input that determines when V enough for a session to start ...
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... NXP Semiconductors 7.10.2 V CC(I/O) The input power pin that sets the I/O voltage level. For details, see and Section • CLOCK • DATA[7:0] • DIR • NXT • RESET_N • STP 7.10.3 RREF Resistor reference analog I/O pin. A resistor, R and GND, as shown in biases internal analog circuitry ...
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... NXP Semiconductors 7.10.7 REG3V3 and REG1V8 Regulator output voltage. These supplies are used to power the ISP1505 internal digital and analog circuits, and must not be used to power external circuits. For correct operation of the regulator recommended that you connect REG3V3 and REG1V8 to decoupling capacitors. For an example, see 7 ...
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... NXP Semiconductors 7.10.10 DIR ULPI direction output pin. Controls the direction of the data bus. By default, the ISP1505 holds DIR at LOW, causing the data bus input. When DIR is LOW, the ISP1505 listens for data from the link. The ISP1505 pulls DIR to HIGH only when it has data to send to the link, which is for one of two reasons: • ...
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... NXP Semiconductors 8. Modes of operation 8.1 ULPI modes The ISP1505 ULPI bus can be programmed to operate in four modes. Each mode reconfigures the signals on the data bus as described in the following subsections. Setting more than one mode will lead to undefined behavior. 8.1.1 Synchronous mode This is default mode ...
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... NXP Semiconductors Table 3. Signal name DIR STP NXT 8.1.2 Low-power mode When the USB is idle, the link can place the ISP1505 into low-power mode (also called suspend mode). In low-power mode, the data bus definition changes to that shown in Table 4. To enter low-power mode, the link sets the SUSPENDM bit in the Function Control register to logic 0 ...
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... NXP Semiconductors Table 4. Signal mapping during low-power mode Signal Maps to Direction Reserved DATA2 O INT DATA3 O Reserved DATA[7:4] O 8.1.3 6-pin full-speed or low-speed serial mode If the link requires a 6-pin serial interface to transmit and receive full-speed or low-speed USB data, it can set the ISP1505 to 6-pin serial mode. In 6-pin serial mode, the DATA[7:0] bus defi ...
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... NXP Semiconductors Table 6. Signal mapping for 3-pin serial mode Signal Maps to TX_ENABLE DATA0 DAT DATA1 SE0 DATA2 INT DATA3 Reserved DATA[7:4] 8.2 USB and OTG state transitions A Hi-Speed USB peripheral, host or OTG device handles more than one electrical state as defined in Universal Serial Bus Specification Rev. 2.0 and On-The-Go Supplement to the USB 2.0 Specifi ...
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... NXP Semiconductors Table 7. Operating states and their corresponding resistor settings Signaling mode Register settings XCVR SELECT [1:0] Host low-speed 10b suspend Host low-speed 10b resume Host Test J or Test K 00b Peripheral settings Peripheral chirp 00b Peripheral 00b high-speed Peripheral full-speed 01b ...
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... NXP Semiconductors 9. Protocol description The following subsections describe the protocol for using the ISP1505. 9.1 ULPI references The ISP1505 provides a 12-pin ULPI interface to communicate with the link highly recommended that you read UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 and UTMI+ Specifi ...
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... NXP Semiconductors If a crystal is attached or a clock is driven into the XTAL1 pin, the ISP1505 will drive a 60 MHz clock out from the CLOCK pin when DIR deasserts. This is shown as CLOCK in Figure 4. The recommended power-up sequence for the link is as follows: 1. The link waits for 1 ms, ignoring all the ULPI pin status. ...
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... NXP Semiconductors CC(I/O) REG1V8 t PWRUP internal REG1V8 detector internal POR XTAL1 CLOCK DATA[7:0] DIR STP NXT and V are applied to the ISP1505. The ISP1505 regulator starts to turn on. CC CC(I/ ULPI pads detect REG1V8 rising above the REG1V8 regulator threshold and are not in 3-state. These pads may drive either LOW or HIGH recommended that the link ignores the ULPI pins status during The POR threshold is reached and a POR pulse is generated. After the POR pulse, ULPI pins are driven to a defi ...
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... NXP Semiconductors The interface protect feature can be disabled by setting the INTF_PROT_DIS bit to logic 1. 9.3.2 Interface behavior with respect to RESET_N The use of the RESET_N pin is optional. When RESET_N is asserted (LOW), the ISP1505 will assert DIR. All logic in the ISP1505 will be reset, including the analog circuitry and ULPI registers. During reset, the link must drive DATA[7:0] and STP to LOW ...
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... NXP Semiconductors The FAULT input pin is mapped to the A_VBUS_VLD bit in RXCMD. Any changes for the FAULT input will trigger RXCMD carrying the FAULT condition with A_VBUS_VLD. 9.5 TXCMD and RXCMD Commands between the ISP1505 and the link are described in the following subsections. ...
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... NXP Semiconductors Table 9. RXCMD byte format DATA Name Description and value LINESTATE LINESTATE signals: For a definition of LINESTATE, see DATA0 — LINESTATE[0] DATA1 — LINESTATE[ state Encoded V BUS RxEvent Encoded USB event signals: For an explanation of RxEvent, see 6 reserved - 7 ALT_INT By default, this signal is not used and is not needed in typical designs. Optionally, the link can enable the BVALID_RISE and/or BVALID_FALL bits in the Power Control register ...
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... NXP Semiconductors Table 11. LINESTATE[1:0] encoding for downstream facing ports: host DP_PULLDOWN and DM_PULLDOWN = 1. Mode Low-speed XCVRSELECT[1:0] 10 TERMSELECT 1 OPMODE[1:0] X LINESTATE[1:0] 00 SE0 01 LS-K 10 LS-J 11 SE1 [1] !squelch indicates inactive squelch. !HS_Differential_Receiver_Output indicates inactive HS_Differential_Receiver_Output. 9.5.2.2 V state encoding BUS USB devices must monitor the V starting a session and SRP. The V ...
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... NXP Semiconductors V /FAULT BUS IND_COMPL USE_EXT_VBUS_IND, IND_PASSTHRU Fig 7. RXCMD A_VBUS_VLD indicator source 9.5.2.3 Using and selecting the V The V BUS link whenever there is a change in the V must first enable the corresponding interrupts in the USB Interrupt Enable Rising Edge and USB Interrupt Enable Falling Edge registers. ...
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... NXP Semiconductors OTG devices: that supplies less than 100 pin. The internal A_VBUS_VLD comparator can be used. If the OTG A-device provides more than 100 USB host controllers” on page 25 detect when an OTG B-device is initiating V When an OTG device is configured as an OTG B-device, SESS_VLD must be used to ...
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... NXP Semiconductors 9.6 Register read and write operations Figure 8 addressing and extended addressing register operations. Extended register addressing is optional for links. Note that register operations will be aborted if the ISP1505 unexpectedly asserts DIR during the operation. When a register operation is aborted, the link must retry until successful. For more information on register operations, refer to UTMI+ Low Pin Interface (ULPI) Specifi ...
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... NXP Semiconductors than 7 ms after reset time T up its clock within 5.6 ms, leaving 200 s for the link to start transmitting the Chirp K, and 1.2 ms for the Chirp K to complete (worst case with 10 % slow clock). b. Host chirp: If the host does not detect the peripheral chirp, it must continue asserting SE0 until the end of reset ...
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... NXP Semiconductors USB reset T 0 TXCMD (REGW) SE0 DATA [ 7:0 ] DIR STP NXT 01 (FS) XCVR SELECT TERM SELECT 00 (normal) OP MODE J (01b) SE0 (00b) LINE STATE TXCMD SE0 (REGW) DATA [ 7:0 ] DIR STP NXT 01 (FS) XCVR SELECT TERM SELECT 00 (normal) OP MODE J (01b) ...
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... NXP Semiconductors 9.8 USB packet transmit and receive An example of a packet transmit and receive is shown in packets, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 . link sends TXCMD CLOCK DATA [ 7:0 ] TXCMD DIR STP NXT Fig 10. Example of using the ISP1505 to transmit and receive USB data 9 ...
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... NXP Semiconductors Table 16. Link decision times Packet sequence High-speed link delay Transmit-Transmit (host only) Receive-Transmit (host or peripheral) Receive-Receive 1 (peripheral only) Transmit-Receive 92 (host or peripheral DATA DM CLOCK DATA [7:0] DIR STP NXT TX end delay (two to five clocks) Fig 11. High-speed transmit-to-transmit packet timing ISP1505A_ISP1505C_3 ...
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... NXP Semiconductors DP or DATA EOP DM CLOCK DATA [7: DIR STP NXT RX end delay (three to eight clocks) Fig 12. High-speed receive-to-transmit packet timing 9.9 Preamble Preamble packets are headers to low-speed packets that must travel over a full-speed bus, between a host and a hub. To enter preamble mode, the link sets XCVRSELECT[1:0] = 11b in the Function Control register ...
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... NXP Semiconductors CLOCK DATA[7: Fig 13. Preamble sequence 9.10 USB suspend and resume 9.10.1 Full-speed and low-speed host-initiated suspend and resume Figure 14 suspend and sometime later initiates resume signaling to wake up the downstream peripheral. Note that LINESTATE updates. The sequence of events for a host and a peripheral, both with ISP1505 follows: 1 ...
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... NXP Semiconductors idle DATA [ 7:0 ] DIR STP NXT OPMODE 00b LINE STATE CLOCK TXCMD (REGW) DATA [ 7:0 ] DIR STP NXT OPMODE SUSPENDM LINE STATE DP DM Timing is not to scale. Fig 14. Full-speed suspend and resume 9.10.2 High-speed suspend and resume Figure 15 suspend and then initiates resume signaling. The high-speed peripheral will wake up and return to high-speed operations ...
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... NXP Semiconductors The sequence of events related to a host and a peripheral, both with ISP1505 follows: 1. High-speed idle: Initially, the host and the peripheral are idle. The host has its 15 k pull-down resistors enabled (DP_PULLDOWN and DM_PULLDOWN are set to 1b) and Full-speed suspend: When the peripheral sees no bus activity for 3 ms, it enters the suspend state ...
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... NXP Semiconductors HS idle TXCMD (REGW) DATA [ 7:0 ] DIR STP NXT XCVR 00b SELECT TERM SELECT OP MODE !SQUELCH SQUELCH (00b) (01b) LINE STATE CLOCK TXCMD (REGW) DATA [ 7:0 ] DIR STP NXT XCVR 00b SELECT TERM SELECT OP MODE SUSPENDM !SQUELCH SQUELCH (01b) (00b) ...
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... NXP Semiconductors 9.10.3 Remote wake-up The ISP1505 supports peripherals that initiate remote wake-up resume. When placed into USB suspend, the peripheral link remembers at what speed it was originally operating. Depending on the original speed, the link follows one of the protocols detailed here. In Figure 16, timing is not to scale, and not all RXCMD LINESTATE updates are shown ...
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... NXP Semiconductors LINESTATE DATA [ 7:0 ] DIR STP NXT XCVR SELECT TERM SELECT OP MODE TXCMD LINESTATE REGW DATA [ 7:0 ] DIR STP NXT XCVR SELECT TERM SELECT OP MODE Timing is not to scale. Fig 16. Remote wake-up from low-power mode 9.11 No automatic SYNC and EOP generation (optional) This setting allows the link to turn off the automatic SYNC and EOP generation, and must be used for high-speed packets only ...
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... NXP Semiconductors PHY will not transmit any EOP. The ISP1505 will also detect if the PID byte is A5h, indicating an SOF packet, and automatically send a long EOP when STP is asserted. To transmit chirp and resume signaling, the link must set OPMODE[1:0] to 10b. CLOCK TXCMD ...
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... NXP Semiconductors 9.12.1 OTG comparators The ISP1505 provides comparators that conform to On-The-Go Supplement to the USB 2.0 Specification Rev. 1.3 requirements of V and V B_SESS_END V B_SESS_VLD are communicated to the link by RXCMDs as described in comparators is described in 9.12.2 Pull-up and pull-down resistors The USB resistors on DP and DM can be used to initiate data-line pulsing SRP. The link must set the required bus state using mode settings given in 9 ...
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... NXP Semiconductors SYNC DATA0 (TX_ENABLE) DATA1 (TX_DAT) DATA2 (TX_SE0) DATA4 (RX_DP) DATA5 (RX_DM) DATA6 (RX_RCV Fig 18. Example of transmit followed by receive in 6-pin serial mode SYNC DATA0 (TX_ENABLE) DATA1 (TX_DAT/ RX_RCV) DATA2 (TX_SE0/ RX_SE0 Fig 19. Example of transmit followed by receive in 3-pin serial mode ISP1505A_ISP1505C_3 Product data sheet ISP1505A ...
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... NXP Semiconductors 9.14 Aborting transfers The ISP1505 supports aborting transfers on the ULPI bus. For details, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1, Section 3.8.4 . 9.15 Avoiding contention on the ULPI data bus Because the ULPI data bus is bidirectional, avoid situations in which both the link and the PHY simultaneously drive the data bus ...
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... NXP Semiconductors 10. Register map Table 17. Immediate register set overview Field name Immediate register set Vendor ID Low register Vendor ID High register Product ID Low register Product ID High register Function Control register Interface Control register OTG Control register USB Interrupt Enable Rising Edge register ...
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... NXP Semiconductors 10.1 Immediate register set 10.1.1 Vendor ID and Product ID registers 10.1.1.1 Vendor ID Low register Table 19 Table 19. Vendor ID Low register (address R = 00h) bit description Bit Symbol Access Value VENDOR_ID_ R LOW[7:0] 10.1.1.2 Vendor ID High register The bit description of the register is given in Table 20. ...
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... NXP Semiconductors Table 24. Function Control register (address R = 04h to 06h 04h 05h 06h) bit description Bit Symbol Description 7 - reserved 6 SUSPENDM Suspend LOW: Active LOW PHY suspend. Places the PHY into low-power mode. The PHY will power down all blocks, except the full-speed receiver, OTG comparators and ULPI interface pins. ...
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... NXP Semiconductors Table 26. Interface Control register (address R = 07h to 09h 07h 08h 09h) bit description Bit Symbol Description 7 INTF_PROT_DIS Interface Protect Disable: Controls circuitry built into the ISP1505 to protect the ULPI interface when the link 3-states STP and DATA[7:0]. When this bit is enabled, the ISP1505 will automatically detect when the link stops driving STP. 0b — ...
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... NXP Semiconductors Table 28. OTG Control register (address R = 0Ah to 0Ch 0Ah 0Bh 0Ch) bit description Bit Symbol Description 7 USE_EXT_VBUS_ Use External V IND 0b — Use the internal OTG comparator. 1b — Use the external V 6 DRV_VBUS_EXT Drive V 0b — Do not drive PSW_N to LOW, disabling V 1b — ...
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... NXP Semiconductors Table 30. USB Interrupt Enable Rising Edge register (address R = 0Dh to 0Fh 0Dh 0Eh 0Fh) bit description Bit Symbol Description reserved 3 SESS_END_R Session End Rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on SESS_END. 2 SESS_VALID_R Session Valid Rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on SESS_VLD ...
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... NXP Semiconductors Table 34. USB Interrupt Status register (address R = 13h) bit description Bit Symbol SESS_END 2 SESS_VALID 1 VBUS_VALID 0 HOST_DISCON 10.1.8 USB Interrupt Latch register The bits of the USB Interrupt Latch register are automatically set by the ISP1505 when an unmasked change occurs on the corresponding interrupt source signal. The ISP1505 will automatically clear all bits when the link reads this register, or when the PHY enters low-power mode ...
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... NXP Semiconductors Table 38. Debug register (address R = 15h) bit description Bit Symbol LINESTATE1 0 LINESTATE0 10.1.10 Scratch register Table 39 purposes. Table 39. Scratch register (address R = 16h to 18h 16h 17h 18h) bit description Bit Symbol Access SCRATCH R/W/S/C [7:0] 10.1.11 Reserved Registers 19h to 2Eh are not implemented. Operating on these addresses will have no effect on the PHY ...
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... NXP Semiconductors Table 41. Power Control register (address R = 3Dh to 3Fh 3Dh 3Eh 3Fh) bit description Bit Symbol Description reserved; the link must never write logic 1 to these bits. 3 BVALID_FALL BVALID Fall: Enables RXCMDs for HIGH-to-LOW transitions on BVALID. When BVALID changes from HIGH to LOW, the ISP1505 will send an RXCMD to the link with the ALT_INT bit set to logic 1 ...
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... NXP Semiconductors 11. ElectroStatic Discharge (ESD) 11.1 ESD protection The pins that are connected to the USB connector (DP, DM, V minimum ESD protection. Capacitors 0.1 F and 1 F must be connected in parallel from V Remark: Capacitors 0.1 F and 1 F are also required by Universal Serial Bus Specification Rev. 2.0 . For details on the requirements for C ...
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... NXP Semiconductors 12. Limiting values Table 42. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage CC V input/output supply voltage CC(I/O) V input voltage I V electrostatic discharge ESD voltage I latch-up current lu V latch-up voltage lu T storage temperature stg The ISP1505 has been tested according to the additional requirements listed in Universal Serial Bus Specifi ...
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... NXP Semiconductors 14. Static characteristics Table 44. Static characteristics: supply pins CC(I/O) Typical values are 3 Symbol Parameter V voltage on pin REG3V3 (REG3V3) V voltage on pin REG1V8 (REG1V8) V power-on reset trip POR(trip) voltage I supply current CC I supply current on CC(I/O) pin V CC(I/O) [1] A continuous stream packets with minimum inter-packet gap and all data bits set to logic 0 for continuous toggling. ...
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... NXP Semiconductors Table 45. Static characteristics: digital pins (CLOCK, DIR, STP, NXT, DATA[7:0], RESET_N/PSW_N CC(I/O) Typical values are 3 Symbol Parameter Impedance Z load impedance L Pull-up and pull-down I pull-down current pd I pull-up current pu Capacitance C input capacitance in Table 46. Static characteristics: pin CC(I/O) Applicable only when pin V /FAULT is used as FAULT ...
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... NXP Semiconductors Table 47. Static characteristics: analog I/O pins (DP CC(I/O) Typical values are 3 Symbol Parameter Termination V termination voltage for upstream TERM facing port pull-up Resistance R pull-up resistance on pin DP UP(DP) High-speed USB transceiver Input levels (differential receiver) V high-speed squelch detection ...
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... NXP Semiconductors Table 48. Static characteristics CC(I/O) Typical values are 3 Symbol Parameter V A-device V A_VBUS_VLD BUS V B-device session valid voltage B_SESS_VLD V B-device session valid hysteresis hys(B_SESS_VLD) voltage V B-device session end voltage B_SESS_END Table 49. Static characteristics CC(I/O) Typical values are 3.3 V ...
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... CC(I/O) amb Conditions 4 capacitor each on pins REG1V8 and REG3V3 ISP1505ABS ISP1505CBS ISP1505ABS ISP1505CBS applicable only when clock is applied on pin XTAL1 only for square wave input only for square wave input only for square wave input measured from power good or assertion of pin STP ...
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... NXP Semiconductors Table 52. Dynamic characteristics: digital I/O pins +85 C; unless otherwise specified. CC amb Symbol Parameter t DATA output delay with respect d(DATA) to the rising edge of pin CLOCK t STP set-up time with respect to su(STP) the rising edge of pin CLOCK t STP hold time with respect to ...
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... NXP Semiconductors Table 53. Dynamic characteristics: analog I/O pins (DP CC(I/O) Symbol Parameter t transition time: fall time LF t rise and fall time matching LRFM Driver timing t driver propagation delay PLH(drv) (LOW to HIGH) t driver propagation delay PHL(drv) (HIGH to LOW) t driver disable delay from ...
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... NXP Semiconductors HSR Fig 21. Rise time and fall time 1.8 V logic 0.9 V input PZH t PZL V OH differential V CRS data lines V OL Fig 23. Timing of TX_ENABLE to DP and DM 15.1 ULPI timing ULPI interface timing requirements are given in synchronous mode only. All timing is measured with respect to the ISP1505 CLOCK pin. ...
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... NXP Semiconductors 16. Application information Table 54. Recommended bill of materials [1] Designator Application C highly recommended for all bypass applications C highly recommended for all filter applications C mandatory for peripherals VBUS mandatory for host mandatory for OTG D recommended for all ESD ESD-sensitive applications R recommended; for applications ...
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... SHIELD 5 C VBUS A1 SHIELD 6 IP4359CX4/LF SHIELD B1 7 SHIELD 8 (1) Frequency is version dependent: ISP1505ABS: 19.2 MHz; ISP1505CBS: 26 MHz. Fig 26. Using the ISP1505 with a USB host controller; external 5 V source with built-in FAULT and external crystal V V CC(I/ bypass DATA1 1 DATA0 2 V CC(I/O) ...
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... STANDARD-B RECEPTACLE A1 A2 SHIELD 5 IP4359CX4/LF SHIELD ESD SHIELD 7 SHIELD C VBUS 8 f i(XTAL1) (1) Frequency is version dependent: ISP1505ABS: 19.2 MHz; ISP1505CBS: 26 MHz. Fig 27. Using the ISP1505 with a peripheral controller; external square wave input on pin XTAL1 V CC(I/ bypass DATA1 1 24 DATA0 CC(I/ RREF RREF ...
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... NXP Semiconductors 17. Package outline HVQFN24: plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 0.85 mm terminal 1 index area terminal 1 24 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors 18. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 18.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 18.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 29. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 19. Abbreviations Table 57. Acronym ASIC ATX CD-RW EOP ESD ESR FS HBM HNP HS ID IEC LS MO ...
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... NXP Semiconductors Table 57. Acronym PID PLD PLL POR RoHS RXCMD SE0 SOF SRP STB SYNC TTL TXCMD USB USB-IF ULPI UTMI UTMI+ 20. References [1] Universal Serial Bus Specification Rev. 2.0 [2] On-The-Go Supplement to the USB 2.0 Specification Rev. 1.3 [3] UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 [4] UTMI+ Specifi ...
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... NXP Semiconductors 21. Revision history Table 58. Revision history Document ID Release date ISP1505A_ISP1505C_3 20080826 • Modifications: Changed On-The-Go Supplement to the USB 2.0 Specification from Rev. 1.2 to Rev. 1.3. • Section 2 • Section 8.2 “USB and OTG state • Section “OTG • ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 24. Tables Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .3 Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5 Table 3. ULPI signal description . . . . . . . . . . . . . . . . . .13 Table 4. Signal mapping during low-power mode . . . . .14 Table 5. Signal mapping for 6-pin serial mode . . . . . . .15 Table 6. Signal mapping for 3-pin serial mode . . . . . . .16 Table 7. Operating states and their corresponding resistor settings . . . . . . . . . . . . . . . . . . . . . . . .16 Table 8 ...
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... NXP Semiconductors 25. Figures Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Fig 2. Pin configuration HVQFN24; top view . . . . . . . . . .5 Fig 3. Internal power-on reset timing . . . . . . . . . . . . . . .18 Fig 4. Power-up and reset sequence required before the ULPI bus is ready for use . . . . . . . . . .20 Fig 5. Interface behavior with respect to RESET_N .21 Fig 6. Single and back-to-back RXCMDs from the ISP1505 to the link ...
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... NXP Semiconductors 26. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Functional description . . . . . . . . . . . . . . . . . . . 7 7.1 ULPI interface controller . . . . . . . . . . . . . . . . . . 7 7.2 USB data serializer and deserializer 7.3 Hi-Speed USB (USB 2.0) ATX . . . . . . . . . . . . . 7 7 ...
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... NXP Semiconductors 10.1.1.4 Product ID High register . . . . . . . . . . . . . . . . . 44 10.1.2 Function Control register . . . . . . . . . . . . . . . . 44 10.1.3 Interface Control register . . . . . . . . . . . . . . . . 45 10.1.4 OTG Control register . . . . . . . . . . . . . . . . . . . 46 10.1.5 USB Interrupt Enable Rising Edge register . . 47 10.1.6 USB Interrupt Enable Falling Edge register . . 48 10.1.7 USB Interrupt Status register . . . . . . . . . . . . . 48 10.1.8 USB Interrupt Latch register . . . . . . . . . . . . . . 49 10 ...