CY24239PVC

... Clock Control Control CLK_STOP# Stop Clock Control PLL 1 ÷2,3,4 Stop Clock Control SDATA SMBus SCLK Logic PLL2 Stop Clock SDRAMIN Control Intel is a registered trademark of Intel Corporation. Cypress Semiconductor Corporation Document #: 38-07038 Rev. ** Table 2. Pin Selectable Frequency Input Address FS3 FS2 ...

Pin Definitions Pin Pin Name Pin No. Type CPU1:2 51 CPU_F 52 O PCI1:5 11, 12, 13, 14 PCI0/FS3 9 I/O PCI_F/MODE 8 I/O CLK_STOP IOAPIC_F 54 O IOAPIC0 55 I/O 48MHz/FS1 29 I/O ...

Functional Description I/O Pin Operation Pins 29, and 30 are dual-purpose l/O pins. Upon power- up these pins act as logic inputs, allowing the determination of assigned device functions. A short time after power-up, the logic state ...

Spread Spectrum Frequency Timing Generator The device generates a clock that is frequency modulated in order to increase the bandwidth that it occupies. By increasing the bandwidth of the fundamental and its harmonics, the am- plitudes of the radiated electromagnetic ...

Serial Data Interface The CY24239 features a two-pin, serial data interface that can be used to configure internal register settings that control par- ticular device functions. Upon power-up, the CY24239 initial- izes with default register settings, therefore the use of ...

Writing Data Bytes Each bit in Data Bytes 0–7 controls a particular device function except for the “reserved” bits which must be written as a logic 0. Bits are written MSB (most significant bit) first, which is bit 7. Table ...

Table 5. Data Bytes 0–7 Serial Configuration Map (continued) Affected Pin Bit(s) Pin No. Pin Name 2 22, 21, SDRAM8:11 19 39, 38, SDRAM4:7 36 44, 43, SDRAM0:3 41, 40 Data Byte ...

Table 6. Additional Frequency Selections through Serial Data Interface Data Bytes Input Conditions Data Byte 0, Bit Bit 2 Bit 6 Bit 5 SEL_3 SEL_2 SEL_1 ...

Absolute Maximum Ratings Stresses greater than those listed in this table may cause per- manent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions . Parameter ...

DC Electrical Characteristics: Parameter Description Crystal Oscillator V X1 Input Threshold Voltage TH C Load Capacitance, Imposed on LOAD [6] External Crystal C X1 Input Capacitance IN,X1 Pin Capacitance/Inductance C Input Pin Capacitance IN C Output Pin Capacitance OUT L ...

PCI Clock Outputs, PCI0:5 (Lump Capacitance Test Load = 30 pF) Parameter Description t Period P t High Time H t Low Time L t Output Rise Edge Rate R t Output Fall Edge Rate F t Duty Cycle D ...

SDRAM 0:16 Clock Outputs (Lump Capacitance Test Load = 22 pF) Parameter Description t Period Measured on rising edge at 1. High Time Duration of clock cycle above 2. Low Time Duration of clock cycle below ...

... Power-up (cold start Output Impedance o Ordering Information Ordering Code Package Type CY24239PVC 56-pin SSOP (300 mils) Document #: 38-07038 Rev. ** Test Condition/Comments Determined by PLL divider ratio (see m/n below) (24.004 – 24)/24 (14.31818 MHz x 57/34 = 24.004 MHz) Measured from 0.4V to 2.4V Measured from 2 ...

... Document #: 38-07038 Rev. ** © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user ...

Document Title:CY24239 Spread Spectrum Frequency Timing Generator Document Number:38-07038 REV. ECN NO. Issue Date ** 106975 05/24/01 Document #: 38-07038 Rev. ** Orig. of Change Description of Change IKA CY24239 New Data Sheet Page ...