DLP-HS-FPGA2 DLP Design Inc, DLP-HS-FPGA2 Datasheet
DLP-HS-FPGA2
Specifications of DLP-HS-FPGA2
Related parts for DLP-HS-FPGA2
DLP-HS-FPGA2 Summary of contents
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... U S FEATURES : • Xilinx XC3S200A-4FTG256C FPGA utilized on the DLP-HS-FPGA • Xilinx XC3S400A-4FTG256C FPGA utilized on the DLP-HS-FPGA2 • Micron 32M x 8 DDR2 SDRAM Memory • Built-In Configuration Loader; Writes the Bit File Directly to SPI Flash via High-Speed USB 2.0 Interface • 63 User I/O Channels: 24 Differential Pairs and 8 Global Clocks • ...
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... Embedded Processor 1.0 INTRODUCTION The DLP-HS-FPGA module is a low-cost, compact prototyping tool that can be used for rapid proof of concept or within educational environments. The module is based on the Xilinx Spartan™ 3A and Future Technology Devices International’s FT2232H Dual-Channel High-Speed USB IC. The DLP-HS-FPGA provides both the beginner as well as the experienced engineer with a rapid path to developing FPGA-based designs. When combined with the free ISE™ ...
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... JTAG and SPI Flash interface ports for connection to Xilinx programming tools. 2.0 REFERENCE DESIGN A 10,000-line reference design is available for the Spartan™ 3A FPGA on the DLP-HS-FPGA to those who purchase the module. The design was written in VHDL and built using the free Xilinx ISE™ ...
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... FPGA. It also handles reset and lock synchronization between internal DCM blocks. The design occupies the following FPGA resources on the DLP-HS-FPGA module’s XC3S200A: The design occupies the following FPGA resources on the DLP-HS-FPGA2 module’s XC3S400A: Rev. 1.3 (March 2011) 4 © ...
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... More reference designs are planned. Please contact DLP Design with any specific requests. 3.0 FPGA SPECIFICATIONS The FPGA device used on the DLP-HS-FPGA is the Xilinx Spartan™ 3A: XC3S200A-4FTG256 • Part Number: XC3S200A-4FTG256C • System Gates: 200,000 • Equivalent Logic Cells: • CLB Array: ...
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... The FPGA device used on the DLP-HS-FPGA2 is the Xilinx Spartan™ 3A: XC3S400A-4FTG256 • Part Number: XC3S400A-4FTG256C • System Gates: 400,000 • Equivalent Logic Cells: • CLB Array: Rows: 40 Columns: 24 Total CLB’s: 896 Total Slices: 3,584 Total Flip Flops: 7,168 Total 4-Input LUT’s: 7,168 • ...
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... Channel B must use the 245 FIFO mode, but it can use either the VCP or D2XX drivers. The VCP drivers make the DLP-HS-FPGA appear as an RS232 port to the host application. The D2XX drivers provide faster throughput, but require working with a *.lib or *.dll library in the host application. ...
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... TEST BIT FILE A test file is provided as a download from the DLP Design website that provides rudimentary access to the I/O features of the DLP-HS-FPGA. The following features are provided: • Ping • Read the High/Low State of the Input-Only Pins • Drive I/O Pins High/Low or Read their High/Low State • ...
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... Device Manager under Ports (COM & LPT). 11.0 USING THE DLP-HS-FPGA Select a power source via Header Pins 23 and 24, and connect the DLP-HS-FPGA to the PC to initiate the loading of USB drivers. The easiest way to do this is to connect Pins 23 and 24 to each other ...
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... If you are using the VCP drivers, begin by opening the COM port, and send multi-byte commands as shown in Table 1 below. There is no need to set the baud rate because the DLP-HS-FPGA uses a parallel interface between the USB IC and the FPGA. (The Ping Command can be used to locate the correct COM port used for communicating with the DLP-HS-FPGA, or you can look in Device Manager to see which port was assigned by Windows ...
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... SDRAM Important Note on DDR2 SDRAM Data Access: DDR2 SDRAM data accesses using the reference design on the DLP-HS-FPGA module are always performed 4 bytes at a time due to the fact that the device is configured for a burst length of four. What this means is that column address Bits 0 and 1 only change the order of the read or write bytes; ...
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... Memory Writes 4 Write bytes to the DDR SDRAM The USER I/O Pin Read/Set/Clear Commands I/O number mapping to the physical I/O pins on the DLP-HS-FPGA board are described in the following table: DLP-HS- I/O Number FPGA Pin 0x00 (0) J1 Pin 2 0x01 (1) J1 Pin 3 0x02 (2) J1 Pin 4 ...
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... Digital Input, Output, Differential Pair 21 Digital Input, Output, Differential Pair 21 Digital Input, Output, Differential Pair 22 Digital Input, Output, Differential Pair 22 Digital Input, Output, Regional Clock J1 3 Digital Input, Output, Regional Clock L1 3 Digital Input, Output M1 3 Digital Input, Output 13 © DLP Design, Inc. ...
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... Digital Input, Output, Differential Pair 23 Digital Input, Output, Differential Pair 23- R16 1 Force Suspend Mode (when enabled) T11 2 Return from Suspend Mode Operation - - +5V input to the DLP-HS-FPGA - - +5V supplied by host PC USB port +3.3V supplied by the onboard DLP-HS FPGA regulator after module enumerated Ground - - 14 © DLP Design, Inc. ...
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... DLP Design website at www.dlpdesign.com/test.shtml. Using this tool, single- and multi-byte commands can be sent to the DLP-HS-FPGA board. Once installed the test application is used as follows: The commands used to interface to the DLP-HS-FPGA are detailed in Section 10 of this datasheet. Rev. 1.3 (March 2011) 15 © DLP Design, Inc. ...
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... MECHANICAL DIMENSIONS IN INCHES (MM) (PRELIMINARY) Rev. 1.3 (March 2011) 16 © DLP Design, Inc. ...
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... SCHEMATICS Schematics for the DLP-HS-FPGA are included on the following three pages: Rev. 1.3 (March 2011) 17 © DLP Design, Inc. ...
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... Rev. 1.3 (March 2011) 18 © DLP Design, Inc. ...
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... Rev. 1.3 (March 2011) 19 © DLP Design, Inc. ...
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... Rev. 1.3 (March 2011) 20 © DLP Design, Inc. ...
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... This product and its documentation are supplied on an as-is basis, and no warranty as to their suitability for any particular purpose is either made or implied. DLP Design, Inc. will not accept any claim for damages whatsoever arising as a result of the use or failure of this product. Your statutory rights are not affected ...