ISPLSI 2064VE-135LT100I LATTICE SEMICONDUCTOR, ISPLSI 2064VE-135LT100I Datasheet

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ISPLSI 2064VE-135LT100I

Manufacturer Part Number
ISPLSI 2064VE-135LT100I
Description
CPLD ispLSI® 2000VE Family 2K Gates 64 Macro Cells 135MHz EECMOS Technology 3.3V 100-Pin TQFP
Manufacturer
LATTICE SEMICONDUCTOR
Datasheet

Specifications of ISPLSI 2064VE-135LT100I

Package
100TQFP
Family Name
ispLSI® 2000VE
Device System Gates
2000
Maximum Propagation Delay Time
10 ns
Number Of User I/os
64
Number Of Logic Blocks/elements
16
Typical Operating Supply Voltage
3.3 V
Maximum Operating Frequency
135 MHz
Operating Temperature
-40 to 85 °C
• SuperFAST HIGH DENSITY PROGRAMMABLE LOGIC
• 3.3V LOW VOLTAGE 2064 ARCHITECTURE
• HIGH-PERFORMANCE E
• IN-SYSTEM PROGRAMMABLE
• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE
• THE EASE OF USE AND FAST SYSTEM SPEED OF
• LEAD-FREE PACKAGE OPTIONS
Copyright © 2004 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
2064ve_09
Features
— 2000 PLD Gates
— 64 and 32 I/O Pin Versions, Four Dedicated Inputs
— 64 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
— Small Logic Block Size for Random Logic
— 100% Functional, JEDEC and Pinout Compatible with
— Interfaces with Standard 5V TTL Devices
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
— 3.3V In-System Programmability (ISP™) Using
— Open-Drain Output Option for Flexible Bus Interface
— Increased Manufacturing Yields, Reduced Time-to-
— Reprogram Soldered Devices for Faster Prototyping
PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAs
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
f
t
Boundary Scan Test Access Port (TAP)
Capability, Allowing Easy Implementation of Wired-OR
or Bus Arbitration Logic
Market and Improved Product Quality
Machines, Address Decoders, etc.
ispLSI 2064V Devices
Interconnectivity
max = 280MHz Maximum Operating Frequency
pd = 3.5ns Propagation Delay
2
CMOS
®
TECHNOLOGY
1
The ispLSI 2064VE is a High Density Programmable
Logic Device available in 64 and 32 I/O-pin versions. The
device contains 64 Registers, four Dedicated Input pins,
three Dedicated Clock Input pins, two dedicated Global
OE input pins and a Global Routing Pool (GRP). The
GRP provides complete interconnectivity between all of
these elements. The ispLSI 2064VE features in-system
programmability through the Boundary Scan Test Ac-
cess Port (TAP) and is 100% IEEE 1149.1 Boundary
Scan Testable. The ispLSI 2064VE offers non-volatile
reprogrammability of the logic, as well as the intercon-
nect, to provide truly reconfigurable systems.
The basic unit of logic on the ispLSI 2064VE device is the
Generic Logic Block (GLB). The GLBs are labeled A0,
A1…B7 (see Figure 1). There are a total of 16 GLBs in the
ispLSI 2064VE device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
Functional Block Diagram
Description
A0
A2
A3
A1
High Density SuperFAST™ PLD
A4
GLB
ispLSI
3.3V In-System Programmable
Output Routing Pool (ORP)
B7
A5
Global Routing Pool
Output Routing Pool (ORP)
Logic
Array
Input Bus
(GRP)
D Q
D Q
D Q
D Q
B6
Input Bus
A6
®
B5
A7
2064VE
B4
August 2004
B0
B3
B2
B1
0139A/2064V

Related parts for ISPLSI 2064VE-135LT100I

ISPLSI 2064VE-135LT100I Summary of contents

Page 1

... Scan Testable. The ispLSI 2064VE offers non-volatile reprogrammability of the logic, as well as the intercon- nect, to provide truly reconfigurable systems. The basic unit of logic on the ispLSI 2064VE device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1…B7 (see Figure 1). There are a total of 16 GLBs in the ispLSI 2064VE device ...

Page 2

... Functional Block Diagram Figure 1. ispLSI 2064VE Functional Block Diagram (64-I/O and 32-I/O Versions) Input Bus Output Routing Pool (ORP) Megablock I I/O 2 I/O 3 I/O 4 I/O 5 Global Routing Pool A1 I/O 6 (GRP) I/O 7 I I/O 10 I/O 11 I/O 12 I I/O 15 TDI/IN 0 ...

Page 3

... Capacitance (TA=25°C, f=1.0 MHz) SYMBOL PARAMETER C Dedicated Input Capacitance 1 C I/O Capacitance 2 C Clock and Global Output Enable Capacitance 3 Erase Reprogram Specifications PARAMETER Erase/Reprogram Cycles Specifications ispLSI 2064VE 1 -0.5 to +5.4V PARAMETER Commercial T = 0° 70°C A Industrial T = -40° 85°C A TYPICAL MINIMUM 10000 3 MIN ...

Page 4

... Refer to the Power Consumption CC section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum Specifications ispLSI 2064VE Figure 2. Test Load GND to 3.0V ≤ 1.5 ns 10% to 90% 1.5V 1.5V ...

Page 5

... External Synchronous Clock Pulse Duration, Low wl 1. Unless noted otherwise, all parameters use a GRP load of four, 20 PTXOR path, ORP and Y0 clock. 2. Standard 16-bit counter using GRP feedback. 3. Reference Switching Test Conditions section. Specifications ispLSI 2064VE Over Recommended Operating Conditions 1 DESCRIPTION 2 1 ...

Page 6

... External Synchronous Clock Pulse Duration, Low wl 1. Unless noted otherwise, all parameters use a GRP load of four, 20 PTXOR path, ORP and Y0 clock. 2. Standard 16-bit counter using GRP feedback. 3. Reference Switching Test Conditions section. Specifications ispLSI 2064VE Over Recommended Operating Conditions 1 DESCRIPTION 2 1 ...

Page 7

... Global Reset to GLB gr 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros. Specifications ispLSI 2064VE 1 Over Recommended Operating Conditions DESCRIPTION 3 ...

Page 8

... Global Reset to GLB gr 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros. Specifications ispLSI 2064VE 1 Over Recommended Operating Conditions DESCRIPTION 3 ...

Page 9

... Clock (max) + Reg co + Output grp + ptck(max (#20 + #22 + #35) + (#31) + (#36 + #38) 6.3ns = (0.4 + 0.4 + 2.9) + (0.2) + (1.2 + 1.2) Note: Calculations are based on timing specifications for the ispLSI 2064VE-280L. Specifications ispLSI 2064VE GRP GLB Feedback Comb 4 PT Bypass #23 GRP Reg 4 PT Bypass #22 # XOR Delays #25, 26, 27 Control ...

Page 10

... Product Terms Figure 3. Typical Device Power Consumption vs fmax I CC can be estimated for the ispLSI 2064VE using the following equation (mA PTs * 0.67 Nets * Fmax * 0.0045) Where PTs = Number of Product Terms used in design ...

Page 11

... Boundary Scan state machine. (2) When BSCAN is high, it functions as a dedicated clock input. GND Ground (GND) VCC Vcc Connect I/O Input/Output pins – These are the general purpose I/O pins used by the logic array pins are not to be connected to any active signals, VCC or GND. Specifications ispLSI 2064VE Description Description 11 ...

Page 12

... 32-I/O Signal Locations — Specifications ispLSI 2064VE I/O Locations Signal caBGA I I I I I/O 12 I/O 13 I I/O 16 I/O 17 I/O 18 I I I/O 27 I/O 28 I/O 29 I/O 30 I/O 31 I/O 32 I I/O 35 ...

Page 13

... Signal Configuration ispLSI 2064VE 100-Ball caBGA Signal Diagram (0.8mm Ball Pitch/10.0 x 10.0mm Body Size I/O I I/O I I/O I I/O I GOE F VCC 0 TCK/ G GND IN 3 I/O I I/O I I/O I NCs are not to be connected to any active signals, VCC or GND. Note: Ball A1 indicator dot on top side of package. ...

Page 14

... Pin Configuration ispLSI 2064VE 100-Pin TQFP Pinout Diagram (0.5mm Lead Pitch/14.0 x 14.0mm Body Size RESET 11 VCC 12 GOE 1 13 GND 14 BSCAN 15 TDI pins are not to be connected to any active signals, VCC or GND. Specifications ispLSI 2064VE ispLSI 2064VE ...

Page 15

... PLCC Pinout Diagram (0.05in Lead Pitch/0.65 x 0.65in Body Size) I/O 28 I/O 29 I/O 30 I/O 31 GOE1/Y0 VCC BSCAN TDI/IN 0 I/O 0 I/O 1 I/O 2 Pin Configuration ispLSI 2064VE 44-Pin TQFP Pinout Diagram (0.8mm Lead Pitch/10.0 x 10.0mm Body Size) I/O 28 I/O 29 I/O 30 I/O 31 GOE1/Y0 VCC BSCAN TDI/IN 0 I/O 0 I/O 1 I/O 2 Specifications ispLSI 2064VE ...

Page 16

... INDUSTRIAL I/Os ORDERING NUMBER 64 ispLSI 2064VE-135LT100I 32 ispLSI 2064VE-135LT44I 16 Grade Blank = Commercial I = Industrial Package T100 = 100-Pin TQFP TN100 = Lead-Free 100-Pin TQFP B100 = 100-Ball caBGA T44 = 44-Pin TQFP TN44 = Lead-Free 44-Pin TQFP J44 = 44-Pin PLCC ...

Page 17

... Ordering Information (Cont.) Lead-Free Packaging FAMILY fmax (MHz) tpd (ns) 280 3.5 280 3.5 200 4.5 200 4.5 ispLSI 135 7.5 135 7.5 100 10 100 10 FAMILY fmax (MHz) tpd (ns) 135 7.5 ispLSI 135 7.5 Specifications ispLSI 2064VE COMMERCIAL I/Os ORDERING NUMBER ...

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