XC6SLX45T-3FGG484C Xilinx Inc, XC6SLX45T-3FGG484C Datasheet

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XC6SLX45T-3FGG484C

Manufacturer Part Number
XC6SLX45T-3FGG484C
Description
FPGA Spartan®-6 Family 43661 Cells 45nm (CMOS) Technology 1.2V 484-Pin FBGA
Manufacturer
Xilinx Inc
Series
Spartan® 6 LXTr
Datasheet

Specifications of XC6SLX45T-3FGG484C

Package
484FBGA
Family Name
Spartan®-6
Device Logic Cells
43661
Device Logic Units
27288
Number Of Registers
54576
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
296
Ram Bits
2138112
Package / Case
484-BGA
Mounting Type
Surface Mount
Voltage - Supply
1 V ~ 3.6 V
Operating Temperature
0°C ~ 85°C
Number Of I /o
296
Number Of Logic Elements/cells
43661
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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DS162 (v2.0) March 31, 2011
Spartan-6 FPGA Electrical Characteristics
Spartan®-6 LX FPGAs are available in -3, -3N, -2, and -1L speed grades, with -3 having the highest performance.
Spartan-6 LXT FPGAs are available in -3, -3N, and -2 speed grades, with -3 having the highest performance.
Spartan-6 FPGA DC and AC characteristics are specified for both commercial and industrial grades. Except the operating
temperature range or unless otherwise noted, all the DC and AC electrical parameters are the same for a particular speed
grade (that is, the timing characteristics of a -2 speed grade industrial device are the same as for a -2 speed grade
commercial device). However, only selected speed grades and/or devices might be available in the industrial range. The
Spartan-6 FPGA -3N speed grade designates devices that do not support MCB functionality.
All supply voltage and junction temperature specifications are representative of worst-case conditions. The parameters
included are common to popular designs and typical applications.
This Spartan-6 FPGA data sheet, part of an overall set of documentation on the Spartan-6 family of FPGAs, is available on
the Xilinx website.
All specifications are subject to change without notice.
Spartan-6 FPGA DC Characteristics
Table 1: Absolute Maximum Ratings
© 2009–2011 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Zynq, Artix, Kintex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United
States and other countries. All other trademarks are the property of their respective owners.
DS162 (v2.0) March 31, 2011
Preliminary Product Specification
V
IN
Symbol
V
V
and V
V
V
V
CCAUX
CCINT
V
BATT
CCO
REF
FS
TS
(3)
Internal supply voltage relative to GND
Auxiliary supply voltage relative to GND
Output drivers supply voltage relative to GND
Key memory battery backup supply (XC6SLX75, XC6SLX75T, XC6SLX100, XC6SLX100T,
XC6SLX150, and XC6SLX150T only)
External voltage supply for eFUSE programming (XC6SLX75, XC6SLX75T, XC6SLX100,
XC6SLX100T, XC6SLX150, and XC6SLX150T only)
Input reference voltage
I/O input voltage or voltage
applied to 3-state output,
relative to GND
(4)
76
(1)
All user and dedicated
I/Os
Restricted to
maximum of 100 user
I/Os
www.xilinx.com
Description
DC and Switching Characteristics
Commercial
Industrial
Commercial
Industrial
(2)
Spartan-6 FPGA Data Sheet:
DC
20% overshoot duration
8% overshoot duration
DC
20% overshoot duration
4% overshoot duration
20% overshoot duration
15% overshoot duration
10% overshoot duration
20% overshoot duration
10% overshoot duration
8% overshoot duration
Preliminary Product Specification
(5)
(5)
(5)
(5)
–0.60 to 4.10
–0.75 to 4.25
–0.75 to 4.40
–0.60 to 3.95
–0.75 to 4.15
–0.75 to 4.40
–0.75 to 4.35
–0.75 to 4.40
–0.75 to 4.45
–0.75 to 4.25
–0.75 to 4.35
–0.75 to 4.40
–0.5 to 1.32
–0.5 to 3.75
–0.5 to 3.75
–0.5 to 4.05
–0.5 to 3.75
–0.5 to 3.75
Units
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
1

Related parts for XC6SLX45T-3FGG484C

XC6SLX45T-3FGG484C Summary of contents

Page 1

DS162 (v2.0) March 31, 2011 Spartan-6 FPGA Electrical Characteristics Spartan®-6 LX FPGAs are available in -3, -3N, -2, and -1L speed grades, with -3 having the highest performance. Spartan-6 LXT FPGAs are available in -3, -3N, and -2 speed grades, ...

Page 2

Table 1: Absolute Maximum Ratings Symbol T Storage temperature (ambient) STG Maximum soldering temperature (TQG144, CPG196, CSG225, CSG324, CSG484, and FTG256) T SOL Maximum soldering temperature Maximum soldering temperature T Maximum junction temperature j Notes: 1. Stresses beyond those listed ...

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Table 2: Recommended Operating Conditions Symbol Description Maximum current through pin using PCI I/O standard when forward biasing the (10) I clamp diode. IN Battery voltage relative to GND +85C (XC6SLX75, XC6SLX75T, XC6SLX100, XC6SLX100T, XC6SLX150, and XC6SLX150T only) ...

Page 4

Table 4: DC Characteristics Over Recommended Operating Conditions Symbol V Data retention V voltage (below which configuration data might be lost) DRINT CCINT V Data retention V voltage (below which configuration data might be lost) DRAUX CCAUX I V leakage ...

Page 5

... XC6SLX100 36.0 XC6SLX100T 36.0 XC6SLX150 51.0 XC6SLX150T 51.0 XC6SLX4 1.0 XC6SLX9 1.0 XC6SLX16 2.0 XC6SLX25 2.0 XC6SLX25T 2.0 XC6SLX45 3.0 XC6SLX45T 3.0 XC6SLX75 4.0 XC6SLX75T 4.0 XC6SLX100 5.0 XC6SLX100T 5.0 XC6SLX150 7.0 XC6SLX150T 7.0 www.xilinx.com ). Quiescent j Speed Grade Units -3N -2 -1L 4 ...

Page 6

... Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Device -3 XC6SLX4 2.5 XC6SLX9 2.5 XC6SLX16 3.0 XC6SLX25 4.0 XC6SLX25T 4.0 XC6SLX45 5.0 XC6SLX45T 5.0 XC6SLX75 7.0 XC6SLX75T 7.0 XC6SLX100 9.0 XC6SLX100T 9.0 XC6SLX150 12.0 XC6SLX150T 12.0 ). Industrial (I) grade devices have the same typical values the extended MCB performance range ...

Page 7

SelectIO™ Interface DC Input and Output Levels Table 7: Recommended Operating Conditions for User I/Os Using Single-Ended Standards I/O Standard V, Min LVTTL 3.0 LVCMOS33 3.0 LVCMOS25 2.3 LVCMOS18 1.65 LVCMOS18_JEDEC 1.65 LVCMOS15 1.4 LVCMOS15_JEDEC 1.4 LVCMOS12 1.1 LVCMOS12_JEDEC 1.1 ...

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Table 8: Recommended Operating Conditions for User I/Os Using Differential Signal Standards I/O Standard LVDS_33 LVDS_25 BLVDS_25 MINI_LVDS_33 MINI_LVDS_25 (1) LVPECL_33 LVPECL_25 RSDS_33 RSDS_25 (1) TMDS_33 PPDS_33 PPDS_25 DISPLAY_PORT DIFF_MOBILE_DDR DIFF_HSTL_I DIFF_HSTL_II DIFF_HSTL_III DIFF_HSTL_I_18 DIFF_HSTL_II_18 DIFF_HSTL_III_18 DIFF_SSTL3_I DIFF_SSTL3_II DIFF_SSTL2_I DIFF_SSTL2_II ...

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In Table 9 and Table 10, values for V the recommended operating conditions at the V chosen to ensure that all standards meet their specifications. The selected standards are tested at a minimum V respective V and V voltage levels ...

Page 10

Table 10: Differential I/O Standard DC Input and Output Levels V ID mV, mV, I/O Standard Min Max (2)(3) LVDS_33 100 600 (2)(3) LVDS_25 100 600 (2)(3) BLVDS_25 100 – MINI_LVDS_33 200 600 MINI_LVDS_25 200 600 (2)(3) LVPECL_33 100 1000 ...

Page 11

Read Endurance Table 11 lists the minimum guaranteed number of read cycle operations for Device DNA and for the AES eFUSE key. For more information, see the Spartan-6 FPGA Configuration User Guide. Table 11: eFUSE Read Endurance Symbol DNA_CYCLES ...

Page 12

Table 14: GTP Transceiver Current Supply (per Lane) Symbol I GTP transceiver internal analog supply current MGTAVCC I GTP transmitter termination supply current MGTAVTTTX I GTP receiver termination supply current MGTAVTTRX I GTP transmitter and receiver PLL supply current MGTAVCCPLL ...

Page 13

GTP Transceiver DC Input and Output Levels Table 16 summarizes the DC output specifications of the GTP transceivers in Spartan-6 FPGAs. ended output voltage swing. Figure 2 Consult UG386: Spartan-6 FPGA GTP Transceivers User Guide for further details. Table 16: ...

Page 14

Table 17: GTP Transceiver Clock DC Input Level Specification Symbol V Differential peak-to-peak input voltage IDIFF R Differential input resistance IN C Required external AC coupling capacitor EXT GTP Transceiver Switching Characteristics Consult the Spartan-6 FPGA GTP Transceivers User Guide ...

Page 15

Table 21: GTP Transceiver User Clock Switching Characteristics Symbol Description F TXOUTCLK maximum frequency TXOUT F RXRECCLK maximum frequency RXREC T RXUSRCLK maximum frequency RX T RXUSRCLK2 maximum frequency RX2 T TXUSRCLK maximum frequency TX T TXUSRCLK2 maximum frequency TX2 ...

Page 16

Table 23: GTP Transceiver Receiver Switching Characteristics Symbol T Time for RXELECIDLE to respond to loss or restoration of data RXELECIDLE R OOB detect threshold peak-to-peak XOOBVDPP R Receiver spread-spectrum tracking XSST R Run length (CID) XRL Data/REFCLK PPM offset ...

Page 17

Performance Characteristics This section provides the performance characteristics of some common functions and designs implemented in Spartan-6 devices. The numbers reported here are worst-case values; they have all been fully characterized. These values are subject to the same guidelines as ...

Page 18

... Table 26: Spartan-6 Device Speed Grade Designations Speed Grade Designations Device Advance (1) XC6SLX4 XC6SLX9 XC6SLX16 XC6SLX25 XC6SLX25T XC6SLX45 XC6SLX45T XC6SLX75 XC6SLX75T XC6SLX100 XC6SLX100T XC6SLX150 XC6SLX150T Notes: 1. The XC6SLX4 is not available in the -3N speed grade. www.xilinx.com Preliminary Production ...

Page 19

... All subsequent releases of software and speed specifications are valid. Table 27: Spartan-6 Device Production Software and Speed Specification Release Device XC6SLX4 XC6SLX9 XC6SLX16 XC6SLX25 XC6SLX25T XC6SLX45 XC6SLX45T XC6SLX75 XC6SLX75T XC6SLX100 XC6SLX100T XC6SLX150 XC6SLX150T Notes: 1. Blank entries indicate a device and/or speed grade in advance or preliminary status. ...

Page 20

Table 28: IOB Switching Characteristics I/O Standard LVDS_33 LVDS_25 BLVDS_25 MINI_LVDS_33 MINI_LVDS_25 LVPECL_33 LVPECL_25 RSDS_33 (point to point) RSDS_25 (point to point) TMDS_33 PPDS_33 PPDS_25 PCI33_3 PCI66_3 DISPLAY_PORT I2C SMBUS SDIO MOBILE_DDR HSTL_I HSTL_II HSTL_III HSTL_I _18 HSTL_II _18 HSTL_III ...

Page 21

Table 28: IOB Switching Characteristics (Cont’d) I/O Standard DIFF_SSTL3_I DIFF_SSTL3_II DIFF_SSTL2_I DIFF_SSTL2_II DIFF_SSTL18_I DIFF_SSTL18_II DIFF_SSTL15_II DIFF_MOBILE_DDR LVTTL, QUIETIO LVTTL, QUIETIO LVTTL, QUIETIO LVTTL, QUIETIO LVTTL, QUIETIO LVTTL, QUIETIO ...

Page 22

Table 28: IOB Switching Characteristics (Cont’d) I/O Standard LVCMOS33, Slow LVCMOS33, Slow LVCMOS33, Slow LVCMOS33, Slow LVCMOS33, Slow LVCMOS33, Fast LVCMOS33, Fast LVCMOS33, Fast ...

Page 23

Table 28: IOB Switching Characteristics (Cont’d) I/O Standard LVCMOS18, QUIETIO LVCMOS18, QUIETIO LVCMOS18, Slow LVCMOS18, Slow LVCMOS18, Slow LVCMOS18, Slow LVCMOS18, Slow LVCMOS18, Slow ...

Page 24

Table 28: IOB Switching Characteristics (Cont’d) I/O Standard LVCMOS15, QUIETIO LVCMOS15, QUIETIO LVCMOS15, QUIETIO LVCMOS15, QUIETIO LVCMOS15, QUIETIO LVCMOS15, QUIETIO LVCMOS15, Slow LVCMOS15, Slow ...

Page 25

Table 28: IOB Switching Characteristics (Cont’d) I/O Standard LVCMOS12, QUIETIO LVCMOS12, QUIETIO LVCMOS12, QUIETIO LVCMOS12, Slow LVCMOS12, Slow LVCMOS12, Slow LVCMOS12, Slow LVCMOS12, Slow ...

Page 26

I/O Standard Adjustment Measurement Methodology Input Delay Measurements Table 30 shows the test setup parameters used for measuring input delay. Table 30: Input Delay Measurement Methodology Description LVTTL (Low-Voltage Transistor-Transistor Logic) LVCMOS (Low-Voltage CMOS), 3.3V LVCMOS, 2.5V LVCMOS, 1.8V LVCMOS, ...

Page 27

Output Delay Measurements Output delays are measured using a Tektronix P6245 TDS500/600 probe (< 1 pF) across approximately 4" of FR4 microstrip trace. Standard termination was used for all testing. The propagation delay of the 4" trace is characterized separately ...

Page 28

Table 31: Output Delay Measurement Methodology (Cont’d) Description SSTL, Class II, 2.5V SSTL, Class II, 1.5V LVDS (Low-Voltage Differential Signaling), 2.5V & 3.3V BLVDS (Bus LVDS), 2.5V Mini-LVDS, 2.5V & 3.3V RSDS (Reduced Swing Differential Signaling), 2.5V & 3.3V RSDS_25, ...

Page 29

Table 32: Spartan-6 FPGA V /GND Pairs per Bank CCO Package Devices TQG144 LX CPG196 LX CSG225 LX FT(G)256 LX LX CSG324 LXT LX CSG484 LXT LX FG(G)484 LXT LX45 FG(G)676 LX75, LX100, LX150 LXT LX FG(G)900 LXT DS162 (v2.0) ...

Page 30

Table 33: SSO Limit per V /GND Pair CCO V I/O Standard CCO 1.2V LVCMOS12, LVCMOS12_JEDEC DS162 (v2.0) March 31, 2011 Preliminary Product Specification Spartan-6 FPGA Data Sheet: DC and Switching Characteristics SSO Limit per V All TQG144, CPG196, Drive ...

Page 31

Table 33: SSO Limit per V /GND Pair (Cont’d) CCO V I/O Standard CCO LVCMOS15, LVCMOS15_JEDEC 1.5V HSTL_I HSTL_II HSTL_III DIFF_HSTL_I DIFF_HSTL_II DIFF_HSTL_III (3) SSTL_15_II (3) DIFF_SSTL_15_II DS162 (v2.0) March 31, 2011 Preliminary Product Specification Spartan-6 FPGA Data Sheet: DC ...

Page 32

Table 33: SSO Limit per V /GND Pair (Cont’d) CCO V I/O Standard CCO LVCMOS18, LVCMOS18_JEDEC 1.8V HSTL_I_18 HSTL_II_18 HSTL_III_18 DIFF_HSTL_I_18 DIFF_HSTL_II_18 DIFF_HSTL_III_18 (3) MOBILE_DDR (3) DIFF_MOBILE_DDR (3) SSTL_18_I (3) SSTL_18_II (3) DIFF_SSTL_18_I (3) DIFF_SSTL_18_II DS162 (v2.0) March 31, 2011 ...

Page 33

Table 33: SSO Limit per V /GND Pair (Cont’d) CCO V I/O Standard CCO LVCMOS25 2.5V (3) SSTL_2_I (3) SSTL_2_II (3) DIFF_SSTL_2_I (3) DIFF_SSTL_2_II DS162 (v2.0) March 31, 2011 Preliminary Product Specification Spartan-6 FPGA Data Sheet: DC and Switching Characteristics ...

Page 34

Table 33: SSO Limit per V /GND Pair (Cont’d) CCO V I/O Standard CCO 3.3V LVCMOS33 DS162 (v2.0) March 31, 2011 Preliminary Product Specification Spartan-6 FPGA Data Sheet: DC and Switching Characteristics SSO Limit per V All TQG144, CPG196, Drive ...

Page 35

Table 33: SSO Limit per V /GND Pair (Cont’d) CCO V I/O Standard CCO LVTTL 3.3V PCI33_3 PCI66_3 SSTL_3_I SSTL_3_II DIFF_SSTL_3_I DIFF_SSTL_3_II SDIO DS162 (v2.0) March 31, 2011 Preliminary Product Specification Spartan-6 FPGA Data Sheet: DC and Switching Characteristics SSO ...

Page 36

Table 33: SSO Limit per V /GND Pair (Cont’d) CCO V I/O Standard CCO LVDS_33 LVDS_25 BLVDS_25 MINI_LVDS_33 MINI_LVDS_25 RSDS_33 Various RSDS_25 TMDS_33 PPDS_33 PPDS_25 DISPLAY_PORT I2C SMBUS Notes: 1. SSO limits greater than the number of I/O per V ...

Page 37

Input/Output Logic Switching Characteristics Table 34: ILOGIC2 Switching Characteristics Symbol Setup/Hold T /T CE0 pin Setup/Hold with respect to CLK ICE0CK ICKCE0 pin Setup/Hold with respect to CLK ISRCK ICKSR pin Setup/Hold with respect ...

Page 38

Input Serializer/Deserializer Switching Characteristics Table 36: ISERDES2 Switching Characteristics Symbol Setup/Hold for Control Lines BITSLIP pin Setup/Hold with respect to CLKDIV ISCCK_BITSLIP ISCKC_BITSLIP pin Setup/Hold with respect to CLK ISCCK_CE ISCKC_CE Setup/Hold for ...

Page 39

Input/Output Delay Switching Characteristics Table 38: IODELAY2 Switching Characteristics Symbol CAL pin Setup/Hold with respect to CK IODCCK_CAL IODCKC_CAL pin Setup/Hold with respect to CK IODCCK_CE IODCKC_CE INC pin Setup/Hold ...

Page 40

CLB Switching Characteristics (SLICEM Only) Table 39: CLB Switching Characteristics (SLICEM Only) Symbol Combinatorial Delays T An – Dn LUT inputs outputs ILO An – Dn LUT inputs through F7AMUX/F7BMUX to AMUX/CMUX output T An – ...

Page 41

CLB Distributed RAM Switching Characteristics (SLICEM Only) Table 40: CLB Distributed RAM Switching Characteristics (SLICEM Only) Symbol Sequential Delays T Clock to A – D outputs SHCKO Clock to A – D outputs (direct output path) Setup and Hold Times ...

Page 42

Block RAM Switching Characteristics Table 42: Block RAM Switching Characteristics Symbol Block RAM Clock to Out Delays T Clock CLK to DOUT output (without output register) RCKO_DO T Clock CLK to DOUT output (with output register) RCKO_DO_REG Setup and Hold ...

Page 43

DSP48A1 Switching Characteristics Table 43: DSP48A1 Switching Characteristics Symbol Setup and Hold Times of Data/Control Pins to the Input Register Clock input to A1 register CLK DSPDCK_A_A1REG T DSPCKD_A_A1REG input to B1 register CLK ...

Page 44

Table 43: DSP48A1 Switching Characteristics (Cont’d) Symbol Clock to Out from Output Register Clock to Output Pin T CLK (PREG output DSPCKO_P_PREG Clock to Out from Pipeline Register Clock to Output Pins T CLK (MREG output ...

Page 45

Table 44: Device DNA Interface Port Switching Characteristics Symbol T Setup time on SHIFT before the rising edge of CLK DNASSU T Hold time on SHIFT after the rising edge of CLK DNASH T Setup time on DIN before the ...

Page 46

... XC6SLX100T in x8 mode, XC6SLX150, and XC6SLX150T only) Maximum CCLK frequency (XC6SLX100 and XC6SLX100T in x16 mode only) Maximum Readback CCLK frequency (XC6SLX4, XC6SLX9, XC6SLX16, XC6SLX25, XC6SLX25T, XC6SLX45, XC6SLX45T, XC6SLX75, and XC6SLX75T F only) RBCCK Maximum Readback CCLK frequency (XC6SLX100, XC6SLX100T, XC6SLX150, and XC6SLX150T only) ...

Page 47

... Maximum frequency, serial mode (Master Serial/SPI) MCCK All devices Maximum frequency, parallel mode (Master SelectMAP/BPI) XC6SLX4, XC6SLX9, XC6SLX16, XC6SLX25, XC6SLX25T, XC6SLX45, XC6SLX45T, XC6SLX75, and XC6SLX75T Maximum frequency, parallel mode (Master SelectMAP/BPI) XC6SLX100 and XC6SLX100T in x8 mode, XC6SLX150, and XC6SLX150T Maximum frequency, parallel mode (Master ...

Page 48

Clock Buffers and Networks Table 47: Global Clock Switching Characteristics Symbol T S pin Setup to I0/I1 inputs GSI T BUFGMUX delay from I0/ GIO Maximum Frequency F Global clock tree (BUFG) MAX Table 48: Input/Output Clock Switching ...

Page 49

PLL Switching Characteristics Table 50: PLL Specification Symbol F Maximum Input Clock Frequency from I/O Clock INMAX Maximum Input Clock Frequency from Global Clock F Minimum Input Clock Frequency INMIN F Maximum Input Clock Period Jitter INJITTER F Allowable Input ...

Page 50

DCM Switching Characteristics Table 51: Operating Frequency Ranges and Conditions for the Delay-Locked Loop (DLL) Symbol Input Frequency Ranges CLKIN_FREQ_DLL Frequency of the CLKIN clock input when the CLKDV output is not used. Frequency of the CLKIN clock input when ...

Page 51

Table 52: Switching Characteristics for the Delay-Locked Loop (DLL) Symbol Output Frequency Ranges CLKOUT_FREQ_CLK0 Frequency for the CLK0 and CLK180 outputs. CLKOUT_FREQ_CLK90 Frequency for the CLK90 and CLK270 outputs. CLKOUT_FREQ_2X Frequency for the CLK2X and CLK2X180 outputs. CLKOUT_FREQ_DV Frequency for ...

Page 52

Table 52: Switching Characteristics for the Delay-Locked Loop (DLL) Symbol (3) LOCK_DLL When using the DLL alone: The time from deassertion at the DCM’s reset input to the rising transition at its LOCKED output. When the DCM is locked, the ...

Page 53

Table 54: Switching Characteristics for the Digital Frequency Synthesizer (DFS) for DCM_SP Symbol Output Frequency Ranges Frequency for the CLKFX and CLKOUT_FREQ_FX CLKFX180 outputs (2)(3) Output Clock Jitter Period jitter at the CLKFX and CLKFX180 outputs. When CLKIN < 20 ...

Page 54

Table 55: Switching Characteristics for the Digital Frequency Synthesizer DFS (DCM_CLKGEN) Symbol Output Frequency Ranges (DCM_CLKGEN) CLKOUT_FREQ_FX Frequency for the CLKFX and CLKFX180 outputs CLKOUT_FREQ_FXDV Frequency for the CLKFXDV output (2)(3) Output Clock Jitter CLKOUT_PER_JITT_FX Period jitter at the CLKFX ...

Page 55

Table 55: Switching Characteristics for the Digital Frequency Synthesizer DFS (DCM_CLKGEN) Symbol Spread Spectrum F Frequency of the CLKIN input for CLKIN_FIXED_SPREAD_ fixed spread spectrum SPECTRUM (SPREAD_SPECTRUM = CENTER_LOW_SPREAD/ CENTER_HIGH_SPREAD) (6) T Spread at the CLKFX output for CENTER_LOW_SPREAD fixed ...

Page 56

Table 57: Switching Characteristics for the Phase-Shift Clock in Variable Phase Mode Symbol Phase Shifting Range When CLKIN < 60 MHz, the maximum allowed number of DCM_DELAY_STEP steps for a given CLKIN clock period, where T = CLKIN clock period ...

Page 57

... IOB and CLB flip-flops are clocked by the global clock net. DS162 (v2.0) March 31, 2011 Preliminary Product Specification Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Description Device XC6SLX4 XC6SLX9 XC6SLX16 XC6SLX25 XC6SLX25T XC6SLX45 XC6SLX45T XC6SLX75 XC6SLX75T XC6SLX100 XC6SLX100T XC6SLX150 XC6SLX150T www.xilinx.com Speed Grade -3 -3N -2 -1L 6 ...

Page 58

... DCM output jitter is already included in the timing calculation. DS162 (v2.0) March 31, 2011 Preliminary Product Specification Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Description Device XC6SLX4 XC6SLX9 XC6SLX16 XC6SLX25 XC6SLX25T XC6SLX45 XC6SLX45T XC6SLX75 XC6SLX75T XC6SLX100 XC6SLX100T XC6SLX150 XC6SLX150T www.xilinx.com Speed Grade -3 -3N -2 -1L 4 ...

Page 59

... XC6SLX4 XC6SLX9 XC6SLX16 XC6SLX25 XC6SLX25T XC6SLX45 XC6SLX45T XC6SLX75 XC6SLX75T XC6SLX100 XC6SLX100T XC6SLX150 XC6SLX150T Description Device XC6SLX4 XC6SLX9 XC6SLX16 XC6SLX25 XC6SLX25T XC6SLX45 XC6SLX45T XC6SLX75 XC6SLX75T XC6SLX100 XC6SLX100T XC6SLX150 XC6SLX150T www.xilinx.com Speed Grade -3 -3N -2 -1L 5.03 N/A 7.21 8.05 5.03 6.13 7.21 8.05 5 ...

Page 60

... XC6SLX4 XC6SLX9 XC6SLX16 XC6SLX25 XC6SLX25T XC6SLX45 XC6SLX45T XC6SLX75 XC6SLX75T XC6SLX100 XC6SLX100T XC6SLX150 XC6SLX150T Description Device XC6SLX4 XC6SLX9 XC6SLX16 XC6SLX25 XC6SLX25T XC6SLX45 XC6SLX45T XC6SLX75 XC6SLX75T XC6SLX100 XC6SLX100T XC6SLX150 XC6SLX150T www.xilinx.com Speed Grade -3 -3N -2 -1L 5.49 N/A 7.44 8.55 5.49 6.29 7.44 8.55 5 ...

Page 61

... DCM and PLL output jitter are already included in the timing calculation. DS162 (v2.0) March 31, 2011 Preliminary Product Specification Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Description Device XC6SLX4 XC6SLX9 XC6SLX16 XC6SLX25 XC6SLX25T XC6SLX45 XC6SLX45T XC6SLX75 XC6SLX75T XC6SLX100 XC6SLX100T XC6SLX150 XC6SLX150T www.xilinx.com Speed Grade -3 -3N -2 -1L 5 ...

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... IFF = Input Flip-Flop or Latch. DS162 (v2.0) March 31, 2011 Preliminary Product Specification Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Description Device (2) without DCM XC6SLX4 XC6SLX9 XC6SLX16 XC6SLX25 XC6SLX25T XC6SLX45 XC6SLX45T XC6SLX75 XC6SLX75T XC6SLX100 XC6SLX100T XC6SLX150 XC6SLX150T www.xilinx.com Speed Grade -3 -3N -2 -1L (1) 0.10/ N/A 0 ...

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... Use IBIS to determine any duty-cycle distortion incurred using various standards. DS162 (v2.0) March 31, 2011 Preliminary Product Specification Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Description Device (2) with DCM in XC6SLX4 XC6SLX9 XC6SLX16 XC6SLX25 XC6SLX25T XC6SLX45 XC6SLX45T XC6SLX75 XC6SLX75T XC6SLX100 XC6SLX100T XC6SLX150 XC6SLX150T www.xilinx.com Speed Grade -3 -3N -2 -1L (1) 1 ...

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... Use IBIS to determine any duty-cycle distortion incurred using various standards. DS162 (v2.0) March 31, 2011 Preliminary Product Specification Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Description Device (2) with DCM in XC6SLX4 XC6SLX9 XC6SLX16 XC6SLX25 XC6SLX25T XC6SLX45 XC6SLX45T XC6SLX75 XC6SLX75T XC6SLX100 XC6SLX100T XC6SLX150 XC6SLX150T www.xilinx.com Speed Grade -3 -3N -2 -1L (1) 0 ...

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... Use IBIS to determine any duty-cycle distortion incurred using various standards. DS162 (v2.0) March 31, 2011 Preliminary Product Specification Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Description Device (2) with PLL in XC6SLX4 XC6SLX9 XC6SLX16 XC6SLX25 XC6SLX25T XC6SLX45 XC6SLX45T XC6SLX75 XC6SLX75T XC6SLX100 XC6SLX100T XC6SLX150 XC6SLX150T www.xilinx.com Speed Grade -3 -3N -2 -1L (1) 1 ...

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... Use IBIS to determine any duty-cycle distortion incurred using various standards. DS162 (v2.0) March 31, 2011 Preliminary Product Specification Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Description Device (2) with PLL in XC6SLX4 XC6SLX9 XC6SLX16 XC6SLX25 XC6SLX25T XC6SLX45 XC6SLX45T XC6SLX75 XC6SLX75T XC6SLX100 XC6SLX100T XC6SLX150 XC6SLX150T www.xilinx.com Speed Grade -3 -3N -2 -1L (1) ...

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... Use IBIS to determine any duty-cycle distortion incurred using various standards. DS162 (v2.0) March 31, 2011 Preliminary Product Specification Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Description Device (2) with DCM in XC6SLX4 XC6SLX9 XC6SLX16 XC6SLX25 XC6SLX25T XC6SLX45 XC6SLX45T XC6SLX75 XC6SLX75T XC6SLX100 XC6SLX100T XC6SLX150 XC6SLX150T www.xilinx.com Speed Grade -3 -3N -2 -1L (1) 1 ...

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... DS162 (v2.0) March 31, 2011 Preliminary Product Specification Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Description Device 20. (2) with DCM in XC6SLX4 XC6SLX9 XC6SLX16 XC6SLX25 XC6SLX25T XC6SLX45 XC6SLX45T XC6SLX75 XC6SLX75T XC6SLX100 XC6SLX100T XC6SLX150 XC6SLX150T www.xilinx.com Speed Grade - -1L (1) Using DCM, PLL, and Global Clock Buffer. For ...

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... XC6SLX4 XC6SLX9 XC6SLX16 XC6SLX25 XC6SLX25T XC6SLX45 XC6SLX45T XC6SLX75 XC6SLX75T XC6SLX100 XC6SLX100T XC6SLX150 XC6SLX150T (3) XC6SLX4 XC6SLX9 XC6SLX16 XC6SLX25 XC6SLX25T XC6SLX45 XC6SLX45T XC6SLX75 XC6SLX75T XC6SLX100 XC6SLX100T XC6SLX150 XC6SLX150T LX Family LXT Family www.xilinx.com Speed Grade (1) -3 -3N -2 0.20 N/A 0.20 0.20 0.20 0.20 0.20 ...

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... Device -3 -3N XC6SLX4 0.06 N/A XC6SLX9 0.06 0.06 XC6SLX16 0.06 0.06 XC6SLX25 0.06 0.06 XC6SLX25T 0.06 0.06 XC6SLX45 0.06 0.06 XC6SLX45T 0.06 0.06 XC6SLX75 0.06 0.06 XC6SLX75T 0.06 0.06 XC6SLX100 0.06 0.06 XC6SLX100T 0.06 0.06 XC6SLX150 0.06 0.06 XC6SLX150T 0.06 0.06 www ...

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... Table 76: Package Skew Symbol T Package Skew PKGSKEW DS162 (v2.0) March 31, 2011 Preliminary Product Specification Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Description Device (1) XC6SLX4 XC6SLX9 XC6SLX16 XC6SLX25 XC6SLX25T XC6SLX45 XC6SLX45T XC6SLX75 XC6SLX75T XC6SLX100 XC6SLX100T www.xilinx.com (2) Package Value Units TQG144 N/A ps CPG196 23 ps CSG225 ...

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Table 76: Package Skew (Cont’d) Symbol T Package Skew PKGSKEW Notes: 1. These values represent the worst-case skew between any two SelectIO resources in the package: shortest delay to longest delay from Pad to Ball. 2. Some of these devices ...

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... Description Device XC6SLX4 XC6SLX9 XC6SLX16 XC6SLX25 XC6SLX25T XC6SLX45 XC6SLX45T XC6SLX75 XC6SLX75T XC6SLX100 XC6SLX100T XC6SLX150 XC6SLX150T XC6SLX4 XC6SLX9 XC6SLX16 XC6SLX25 XC6SLX25T XC6SLX45 XC6SLX45T XC6SLX75 XC6SLX75T XC6SLX100 XC6SLX100T XC6SLX150 XC6SLX150T www.xilinx.com Speed Grade -3 -3N -2 -1L 0.57/ N/A 0.95/ 0.27/ 0.94 1.12 1.56 0.40/ ...

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Revision History The following table shows the revision history for this document. Date Version 06/24/09 1.0 Initial Xilinx release. 08/26/09 1.1 Added V V BATT XC6SLX4 in Table 24 values for T to Table 46, page 46 T SMCKCSO (DRP) ...

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... Added Note 4 and updated values in Table 06/24/10 1.6 Production release of XC6SLX45T (-2 and -3 speed grades), XC6SLX16 and XC6SLX45 (-3 speed grade) devices which includes changes to specification v1.08). Added the -3N speed grade, which designates Spartan-6 devices that do not support MCB functionality (specifications are identical to the -3 speed grade) ...

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Date Version 01/10/11 1.11 Production release of XC6SLX4 and XC6SLX9 in the specific speed grades listed in Table 27 grades. Added note 3 to software with speed specification v1.06. Revised -3N definition throughout the document. Added Note 4 to Updated ...

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