LFE2M20E-6FN484C

Manufacturer Part NumberLFE2M20E-6FN484C
DescriptionFPGA LatticeECP2M Family 19000 Cells 90nm (CMOS) Technology 1.2V 484-Pin FBGA
ManufacturerLATTICE SEMICONDUCTOR
LFE2M20E-6FN484C datasheet
 

Specifications of LFE2M20E-6FN484C

Package484FBGAFamily NameLatticeECP2M
Device Logic Units19000Typical Operating Supply Voltage1.2 V
Maximum Number Of User I/os304Ram Bits1246208
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LatticeECP2/M Family Data Sheet
DS1006 Version 03.8, April 2011

LFE2M20E-6FN484C Summary of contents

  • Page 1

    LatticeECP2/M Family Data Sheet DS1006 Version 03.8, April 2011 ...

  • Page 2

    ... Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...

  • Page 3

    ... Lattice Semiconductor Table 1-2. LatticeECP2M (Including “S-Series”) Family Selection Device LUTs (K) sysMEM Blocks (18kb) Embedded Memory (Kbits) Distributed Memory (Kbits) sysDSP Blocks 18x18 Multipliers GPLL+SPLL+DLL Maximum Available I/O Packages and SERDES / I/O Combinations 256-ball fpBGA ( mm) 484-ball fpBGA ( mm) 672-ball fpBGA ( mm) ...

  • Page 4

    ... The LatticeECP2/M devices use 1.2V as their core voltage. © 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...

  • Page 5

    ... Lattice Semiconductor Figure 2-1. Simplified Block Diagram, ECP2-6 Device (Top Level) Programmable Function Units (PFUs) sysDSP Blocks Multiply and Accumulate Support sysMEM Block RAM 18kbit Dual Port sysCLOCK PLLs and DLLs Frequency Synthesis and Clock Alignment Figure 2-2. Simplified Block Diagram, ECP2M20 Device (Top Level) ...

  • Page 6

    ... Lattice Semiconductor PFU Blocks The core of the LatticeECP2/M device consists of PFU blocks, which are provided in two forms, the PFU and PFF. The PFUs can be programmed to perform Logic, Arithmetic, Distributed RAM and Distributed ROM functions. PFF blocks can be programmed to perform Logic, Arithmetic and ROM functions. Except where necessary, the remain- der of this data sheet will use the term PFU to refer to both PFU and PFF blocks ...

  • Page 7

    ... Lattice Semiconductor Figure 2-4. Slice Diagram FXB FXA From Routing CLK LSR * Not in Slice 3 For Slices 0 and 2, memory control signals are generated from Slice 1 as follows: Table 2-2. Slice Signal Descriptions Function Type Input Data signal Input Data signal Input Multi-purpose ...

  • Page 8

    ... Lattice Semiconductor Modes of Operation Each slice has up to four potential modes of operation: Logic, Ripple, RAM and ROM. Logic Mode In this mode, the LUTs in each slice are configured as 4-input combinatorial lookup tables. A LUT4 can have 16 possible input combinations. Any four input logic functions can be generated by programming this lookup table. ...

  • Page 9

    ... Lattice Semiconductor ROM Mode ROM mode uses the LUT logic; hence, Slices 0 through 3 can be used in ROM mode. Preloading is accomplished through the programming interface during PFU configuration. Routing There are many resources provided in the LatticeECP2/M devices to route signals individually or as busses with related control signals ...

  • Page 10

    ... Lattice Semiconductor Figure 2-5. General Purpose PLL (GPLL) Diagram CLKI Input Clock Divider (CLKI) (from routing or external pin) Feedback CLKFB Divider (CLKFB) from CLKOP (PLL internal), from clock net(CLKOP) or from a user clock (pin or logic) RST RSTK Standard PLL (SPLL) Some of the larger devices have two to six Standard PLLs (SPLLs). SPLLs have the same features as GPLLs but without delay adjustment capability ...

  • Page 11

    ... Lattice Semiconductor Delay Locked Loops (DLL) In addition to PLLs, the LatticeECP2/M family of devices has two DLLs per device. CLKI is the input frequency (generated either from the pin or routing) for the DLL. CLKI feeds into the output muxes block to bypass the DLL, directly to the DELAY CHAIN block and (directly or through divider circuit) to the reference input of the Phase Frequency Detector (PFD) input mux ...

  • Page 12

    ... Lattice Semiconductor Table 2-5. DLL Signals Signal I/O CLKI I Clock input from external pin or routing CLKFB I DLL feed input from DLL output, clock net, routing or external pin RSTN I Active low synchronous reset ALUHOLD I Active high freezes the ALU UDDCNTL I Synchronous enable signal (hold high for two cycles) from routing ...

  • Page 13

    ... Lattice Semiconductor The DLLs in the LatticeECP2/M are used to shift the clock in relation to the data for source synchronous inputs. PLLs are used for frequency synthesis and clock generation for source synchronous interfaces. Cascading PLL and DLL blocks allows applications to utilize the unique benefits of both DLLs and PLLs. ...

  • Page 14

    ... Lattice Semiconductor Figure 2-9. Clock Divider Connections CLKOP (GPLL) CLKOP (DLL) CLKOS (GPLL) CLKOS (DLL) Clock Distribution Network LatticeECP2/M devices have eight quadrant-based primary clocks and eight flexible region-based secondary clocks/control signals. Two high performance edge clocks are available on each edge of the device to support high speed interfaces ...

  • Page 15

    ... Lattice Semiconductor Figure 2-10. Primary Clock Sources for ECP2-50 PLL Input SPLL CLK DIV Clock Input Clock Input DLL Input DLL PLL Input GPLL Note: This diagram shows sources for the ECP2-50 device. Smaller LatticeECP2 devices have fewer SPLLs. All LatticeECP2M device have six SPLLs ...

  • Page 16

    ... Lattice Semiconductor Secondary Clock/Control Sources LatticeECP2/M devices derive secondary clocks (SC0 through SC7) from eight dedicated clock input pads and the rest from routing. Figure 2-11 shows the secondary clock sources. Figure 2-11. Secondary Clock Sources From Routing From Routing From Routing ...

  • Page 17

    ... Lattice Semiconductor Edge Clock Sources Edge clock resources can be driven from a variety of sources at the same edge. Edge clock resources can be driven from adjacent edge clock PIOs, primary clock PIOs, PLLs/DLLs and clock dividers as shown in Figure 2-12. Figure 2-12. Edge Clock Sources ...

  • Page 18

    ... Lattice Semiconductor Primary Clock Routing The clock routing structure in LatticeECP2/M devices consists of a network of eight primary clock lines (CLK0 through CLK7) per quadrant. The primary clocks of each quadrant are generated from muxes located in the center of the device. All the clock sources are connected to these muxes. Figure 2-13 shows the clock routing for one quadrant ...

  • Page 19

    ... Lattice Semiconductor this special vertical routing channel and the eight secondary clock regions for the ECP2-50. LatticeECP2 devices have four secondary clocks (SC0 to SC3) which are distrubed to every region. The secondary clock muxes are located in the center of the device. Figure 2-16 shows the mux structure of the secondary clock routing ...

  • Page 20

    ... Lattice Semiconductor Figure 2-16. Secondary Clock Selection 24:1 SC0 4 Secondary Clocks/CE/LSR (SC0 to SC3) per Region Slice Clock Selection Figure 2-17 shows the clock selections and Figure 2-18 shows the control selections for Slice0 through Slice2. All the primary clocks and the four secondary clocks are routed to this clock selection mux. Other signals can be used as a clock input to the slices via routing ...

  • Page 21

    ... Lattice Semiconductor Figure 2-18. Slice0 through Slice2 Control Selection Secondary Clock Edge Clock Routing LatticeECP2/M devices have a number of high-speed edge clocks that are intended for use with the PIOs in the implementation of high-speed interfaces. There are eight edge clocks per device: two edge clocks per edge. Differ- ent PLL and DLL outputs are routed to the two muxes on the left and right sides of the device ...

  • Page 22

    ... Lattice Semiconductor sysMEM Memory LatticeECP2/M devices contains a number of sysMEM Embedded Block RAM (EBR). The EBR consists of an 18- Kbit RAM with dedicated input and output registers. sysMEM Memory Block The sysMEM block can implement single port, dual port or pseudo dual port memories. Each block can be used in a variety of depths and widths as shown in Table 2-6 ...

  • Page 23

    ... Lattice Semiconductor 2. Write Through – A copy of the input data appears at the output of the same port during a write cycle. This mode is supported for all data widths. Memory Core Reset The memory array in the EBR utilizes latches at the A and B output ports. These latches can be reset asynchro- nously or synchronously ...

  • Page 24

    ... Lattice Semiconductor If an EBR is pre-loaded during configuration, the GSR input must be disabled or the release of the GSR during device Wake Up must occur before the release of the device I/Os becomes active. These instructions apply to all EBR RAM and ROM implementations. Note that there are no reset restrictions if the EBR synchronous reset is used and the EBR GSR input is disabled. ...

  • Page 25

    ... Lattice Semiconductor • MULT (Multiply) • MAC (Multiply, Accumulate) • MULTADDSUB (Multiply, Addition/Subtraction) • MULTADDSUBSUM (Multiply, Addition/Subtraction, Accumulate) The number of elements available on each block depends in the width selected from the three available options x9, x18, and x36. A number of these elements are concatenated for highly parallel implementations of DSP functions. ...

  • Page 26

    ... Lattice Semiconductor MULT sysDSP Element This multiplier element implements a multiply with no addition or accumulator nodes. The two operands, A and B, are multiplied and the result is available at the output. The user can enable the input/output and pipeline registers. Figure 2-23 shows the MULT sysDSP element. ...

  • Page 27

    ... Lattice Semiconductor MAC sysDSP Element In this case, the two operands, A and B, are multiplied and the result is added with the previous accumulated value. This accumulated value is available at the output. The user can enable the input and pipeline registers, but the out- put register is always enabled. The output register is used to store the accumulated value. The Accumulators in the DSP blocks in the LatticeECP2/M family can be initialized dynamically ...

  • Page 28

    ... Lattice Semiconductor MULTADDSUB sysDSP Element In this case, the operands A0 and B0 are multiplied and the result is added/subtracted with the result of the multi- plier operation of operands A1 and A2. The user can enable the input, output and pipeline registers. Figure 2-25 shows the MULTADDSUB sysDSP element. ...

  • Page 29

    ... Lattice Semiconductor MULTADDSUBSUM sysDSP Element In this case, the operands A0 and B0 are multiplied and the result is added/subtracted with the result of the multi- plier operation of operands A1 and B1. Additionally the operands A2 and B2 are multiplied and the result is added/ subtracted with the result of the multiplier operation of operands A3 and B3. The result of both addition/subtraction are added in a summation block ...

  • Page 30

    ... Lattice Semiconductor one clock is selected for each input register, pipeline register and output register. Similarly Clock enable (CE) and Reset (RST) are selected from their four respective sources (CE0, CE1, CE2, CE3 and RST0, RST1, RST2, RST3) at each input register, pipeline register and output register. ...

  • Page 31

    ... Lattice Semiconductor IPexpress™ The user can access the sysDSP block via the IPexpress tool, which provides the option to configure each DSP module (or group of modules direct HDL instantiation. In addition, Lattice has partnered with The Math- ® Works to support instantiation in the Simulink mond and ispLEVER to dramatically shorten the DSP design cycle in Lattice FPGAs ...

  • Page 32

    ... Lattice Semiconductor LatticeECP2/M DSP Performance Table 2-11 lists the maximum performance in millions of MAC operations per second (MMAC) for each member of the LatticeECP2/M family. Table 2-11. DSP Performance Device ECP2-6 ECP2-12 ECP2-20 ECP2-35 ECP2-50 ECP2-70 ECP2M20 ECP2M35 ECP2M50 ECP2M70 ECP2M100 For further information about the sysDSP block, please see the list of additional technical information at the end of this data sheet ...

  • Page 33

    ... Lattice Semiconductor Figure 2-28. PIC Diagram TD OPOS1 ONEG1 OPOS0 OPOS2* ONEG0 ONEG2* QNEG0* QNEG1* QPOS0* QPOS1* INCK** INDD INFF IPOS0 IPOS1 CLK CE LSR GSRN ECLK1 ECLK2 DDRCLKPOL* DQSXFER* *Signals are available on left/right/bottom edges only. ** Selected blocks. Two adjacent PIOs can be joined to provide a differential I/O pair (labeled as “T” and “C”) as shown in Figure 2-28. ...

  • Page 34

    ... Lattice Semiconductor Table 2-12. PIO Signals List Name Type CE0, CE1 Control from the core CLK0, CLK1 Control from the core ECLK1, ECLK2 Control from the core LSR Control from the core GSRN Control from routing 2 INCK Input to the core DQS ...

  • Page 35

    ... Lattice Semiconductor By combining input blocks of the complementary PIOs and sharing some registers from output blocks, a gearbox function can be implemented, which takes a double data rate signal applied to PIOA and converts it as four data streams, IPOS0A, IPOS1A, IPOS0B and IPOS1B. Figure 2-29 shows the diagram using this gearbox function. For more information about this topic, please see information regarding additional documentation at the end of this data sheet ...

  • Page 36

    ... Lattice Semiconductor Figure 2-30. Input Register Block Top Edge DI (from sysIO buffer) Fixed Delay Dynamic Delay DEL[3:0] CLK0 (from routing) Note: Simplified version does not show CE and SET/RESET details. *On selected blocks. Output Register Block The output register block provides the ability to register signals from the core of the device before they are passed to the sysI/O buffers ...

  • Page 37

    ... Lattice Semiconductor Figure 2-31. Output and Tristate Block for Left, Right and Bottom Edges TD Tristate Logic ONEG1 OPOS1 Q ONEG0 D * D-Type OPOS0 D-Type CLKA Clock Transfer Registers ECLK1 ECLK2 CLK1 (CLKA) DQSXFER TD Tristate Logic ONEG1 OPOS1 Q D ONEG0 D-Type* OPOS0 D-Type* CLKB ...

  • Page 38

    ... Lattice Semiconductor Figure 2-32. Output and Tristate Block, Top Edge TD ONEG1 ONEG0 ECLK1 ECLK2 CLK1 (CLKA) Note: Simplified version does not show CE and SET/RESET details. Tristate Register Block The tristate register block provides the ability to register tri-state control signals from the core of the device before they are passed to the sysI/O buffers ...

  • Page 39

    ... Lattice Semiconductor Top Edge The PICs on the top edge are different from PIOs on the left, right and bottom edges. PIOs on this edge do not have DDR registers or DQS signals. The exact DQS pins are shown in a dual function in the Logic Signal Connections table in this data sheet. Addi- tional detail is provided in the Signal Descriptions table ...

  • Page 40

    ... Lattice Semiconductor Figure 2-34. DQS Input Routing for the Bottom Edge of the Device DQS DLL Calibrated DQS Delay Block Source synchronous interfaces generally require the input clock to be adjusted in order to correctly capture data at the input register. For most interfaces a PLL is used for this adjustment. However, in DDR memories the clock (referred to as DQS) is not free-running so this approach cannot be used ...

  • Page 41

    ... Lattice Semiconductor Figure 2-35. Edge Clock, DLL Calibration and DQS Local Bus Distribution Spans 16 PIOs I DQS Input 7 I Spans 18 PIOs Note: Bank 8 is not shown. LatticeECP2/M Family Data Sheet I/O Bank 0 I/O Bank 1 DDR_DLL DDR_DLL (Right) (Left) I/O Bank 4 I/O Bank 5 ...

  • Page 42

    ... Lattice Semiconductor Figure 2-36. DQS Local Bus *DQSXFERDEL shifts ECLK1 by 90% and is not associated with a particular PIO. Polarity Control Logic In a typical DDR Memory interface design, the phase relationship between the incoming delayed DQS strobe and the internal system clock (during the READ cycle) is unknown. ...

  • Page 43

    ... Lattice Semiconductor DQSXFER LatticeECP2/M devices provide a DQSXFER signal to the output buffer to assist it in data transfer to DDR memo- ries that require DQS strobe be shifted 90 DQSXFER signal runs the span of the data bus. sysI/O Buffer Each I/O is associated with a flexible buffer referred sysI/O buffer. These buffers are arranged around the periphery of the device in groups referred to as banks. The sysI/O buffers allow users to implement the wide variety of standards that are found in today’ ...

  • Page 44

    ... Lattice Semiconductor Figure 2-37. LatticeECP2 Banks V CCIO7 V REF1(7) V REF2(7) GND V CCIO6 V REF1(6) V REF2(6) GND LatticeECP2/M Family Data Sheet TOP Bank 0 Bank 1 Bank 5 Bank 4 BOTTOM 2-41 Architecture V CCIO2 V REF1(2) V REF2(2) GND V CCIO3 V REF1(3) V REF2(3) GND V CCIO8 GND ...

  • Page 45

    ... Lattice Semiconductor Figure 2-38. LatticeECP2M Banks SERDES V CCIO7 V REF1(7) V REF2(7) GND V CCIO6 V REF1(6) V REF2(6) GND LatticeECP2/M devices contain two types of sysI/O buffer pairs. 1. Top (Bank 0 and Bank 1) sysI/O Buffer Pairs (Single-Ended Outputs Only) The sysI/O buffer pairs in the top banks of the device consist of two single-ended output drivers and two sets of single-ended input buffers (both ratioed and referenced). One of the referenced input buffers can also be con- figured as a differential input.  ...

  • Page 46

    ... Lattice Semiconductor sets of single-ended input buffers (both ratioed and referenced). One of the referenced input buffers can also be configured as a differential input.   The two pads in the pair are described as “true” and “comp”, where the true pad is associated with the positive side of the differential input buffer and the comp (complementary) pad is associated with the negative side of the differential input buffer ...

  • Page 47

    ... Lattice Semiconductor O standards (together with their supply and reference voltages) supported by LatticeECP2/M devices. For further information about utilizing the sysI/O buffer to support a variety of standards please see the the list of additional technical information at the end of this data sheet. Table 2-13. Supported Input Standards ...

  • Page 48

    ... Lattice Semiconductor Table 2-14. Supported Output Standards Output Standard Single-ended Interfaces LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 LVCMOS33, Open Drain LVCMOS25, Open Drain LVCMOS18, Open Drain LVCMOS15, Open Drain LVCMOS12, Open Drain PCI33 HSTL18 Class I, II HSTL15 Class I SSTL3 Class I, II ...

  • Page 49

    ... Lattice Semiconductor SERDES and PCS (Physical Coding Sublayer) LatticeECP2M devices feature channels of embedded SERDES arranged in quads at the corners of the devices. Figure 2-39 shows the position of the quad blocks in relation to the PFU array for LatticeECP2M70 and LatticeECP2M100 devices. Table 2-15 shows the location of Quads for all the devices. ...

  • Page 50

    ... Lattice Semiconductor Each Transmit and Receive channel has its independent power supplies. The Output and Input buffers of each channel also have their own independent power supplies. In addition, there are separate power supplies for PLL, terminating resistor per quad. Figure 2-40. Simplified Channel Block Diagram for SERDES and PCS ...

  • Page 51

    ... Lattice Semiconductor IEEE 1149.1-Compliant Boundary Scan Testability All LatticeECP2/M devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant Test Access Port (TAP). This allows functional testing of the circuit board, on which the device is mounted, through a serial scan path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in and loaded directly onto test nodes, or test data to be captured and shifted out for verification ...

  • Page 52

    ... Lattice Semiconductor for checking soft errors (SED) in SRAM. This SED operation can be run in the background during user mode soft error occurs, during user mode (normal operation) the device can be programmed to either reload from a known good boot image or generate an error signal. For further information about Soft Error Detect (SED) support, please see the list of additional technical documen- tation at the end of this data sheet ...

  • Page 53

    ... Transmit Power Supply CCTX © 2011 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...

  • Page 54

    ... Lattice Semiconductor Symbol 6 V PLL and Reference Clock Buffer Power CCP set to 1.2V, they must be connected to the same power supply as V CCIO CCJ nected to the same power supply as V decoupling. 2. See recommended voltages by I/O standard in subsequent table ramp rate must not exceed 30mV/µs during power-up when transitioning between 0V and 3.3V. ...

  • Page 55

    ... Lattice Semiconductor DC Electrical Characteristics Symbol Parameter Input or I/O Low Leakage Input or I/O High Leakage IH I I/O Active Pull-up Current PU I I/O Active Pull-down Current PD I Bus Hold Low Sustaining Current V BHLS I Bus Hold High Sustaining Current V BHHS Bus Hold Low Overdrive Current 0  V ...

  • Page 56

    ... Lattice Semiconductor LatticeECP2 Supply Current (Standby) Symbol I Core Power Supply Current CC I Auxiliary Power Supply Current CCAUX I GPLL Power Supply Current (per GPLL) CCGPLL I GPLL Power Supply Current (per SPLL) CCSPLL I Bank Power Supply Current (Per Bank) CCIO I VCCJ Power Supply Current CCJ 1 ...

  • Page 57

    ... Lattice Semiconductor LatticeECP2M Supply Current (Standby) Symbol I Core Power Supply Current CC I Auxiliary Power Supply Current CCAUX I GPLL Power Supply Current (per GPLL) CCGPLL I GPLL Power Supply Current (per SPLL) CCSPLL I Bank Power Supply Current (Per Bank) CCIO I V Power Supply Current ...

  • Page 58

    ... Lattice Semiconductor LatticeECP2 Initialization Supply Current Symbol Parameter I Core Power Supply Current CC I Auxiliary Power Supply Current CCAUX I GPLL Power Supply Current (per GPLL) CCGPLL I SPLL Power Supply Current (per SPLL) CCSPLL I Bank Power Supply Current (per Bank) CCIO I VCCJ Power Supply Current CCJ 1 ...

  • Page 59

    ... Lattice Semiconductor LatticeECP2M Initialization Supply Current Symbol I Core Power Supply Current CC I Auxiliary Power Supply Current CCAUX I GPLL Power Supply Current (per GPLL) CCGPLL I SPLL Power Supply Current (per SPLL) CCSPLL I Bank Power Supply Current (per Bank) CCIO I VCCJ Power Supply Current CCJ 1 ...

  • Page 60

    ... Lattice Semiconductor SERDES Power Supply Requirements (LatticeECP2M Family Only) Symbol Standby (Power Down current (per channel) CCTX-SB CCTX I V current (per channel) CCRX-SB CCRX I Input buffer current (per channel) CCIB-SB I Output buffer current (per channel) CCOB-SB I SERDES PLL current (per quad) ...

  • Page 61

    ... Lattice Semiconductor sysI/O Recommended Operating Conditions Standard Min. 2 LVCMOS 3.3 3.135 2 LVCMOS 2.5 2.375 LVCMOS 1.8 1.71 LVCMOS 1.5 1.425 2 LVCMOS 1.2 1.14 2 LVTTL 3.135 PCI 3.135 2 SSTL18 Class I, II 1.71 2 SSTL2 Class I, II 2.375 2 SSTL3 Class I, II 3.135 2 HSTL 15 Class I 1 ...

  • Page 62

    ... Lattice Semiconductor sysI/O Single-Ended DC Electrical Characteristics V IL Input/Output Standard Min. (V) Max. (V) LVCMOS 3.3 -0.3 0.8 LVTTL -0.3 0.8 LVCMOS 2.5 -0.3 0.7 LVCMOS 1.8 -0.3 0.35 V LVCMOS 1.5 -0.3 0.35 V LVCMOS 1.2 -0.3 0.35 V PCI -0.3 0.3 V SSTL3 Class I -0.3 V REF SSTL3 Class II -0 ...

  • Page 63

    ... Lattice Semiconductor sysI/O Differential Electrical Characteristics LVDS Parameter Description Input Voltage INP INM V Input Common Mode Voltage CM V Differential Input Threshold THD I Input Current IN V Output High Voltage for Output Low Voltage for Output Voltage Differential OD Change in V Between High and OD ý ...

  • Page 64

    ... Lattice Semiconductor LVDS25E The top and bottom sides of LatticeECP2/M devices support LVDS outputs via emulated complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The scheme shown in Figure 3-1 is one possible solution for point-to-point signals. Figure 3-1. LVDS25E Output Termination Example VCCIO = 2.5V (± ...

  • Page 65

    ... Lattice Semiconductor BLVDS The LatticeECP2/M devices support the BLVDS standard. This standard is emulated using complementary LVC- MOS outputs in conjunction with a parallel external resistor across the driver outputs. BLVDS is intended for use when multi-drop and bi-directional multi-point differential signaling is required. The scheme shown in Figure 3-2 is one possible solution for bi-directional multi-point differential signals ...

  • Page 66

    ... Lattice Semiconductor LVPECL The LatticeECP2/M devices support the differential LVPECL standard. This standard is emulated using comple- mentary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The LVPECL input stan- dard is supported by the LVDS differential input buffer. The scheme shown in Figure 3-3 is one possible solution for point-to-point signals ...

  • Page 67

    ... Lattice Semiconductor RSDS The LatticeECP2/M devices support differential RSDS standard. This standard is emulated using complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The RSDS input standard is sup- ported by the LVDS differential input buffer. The scheme shown in Figure 3-4 is one possible solution for RSDS standard implementation ...

  • Page 68

    ... Lattice Semiconductor MLVDS The LatticeECP2/M devices support the differential MLVDS standard. This standard is emulated using complemen- tary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The MLVDS input standard is supported by the LVDS differential input buffer. The scheme shown in Figure 3-5 is one possible solution for MLVDS standard implementation ...

  • Page 69

    ... Lattice Semiconductor Typical Building Block Function Performance Pin-to-Pin Performance (LVCMOS25 12mA Drive) Function Basic Functions 16-bit Decoder 32-bit Decoder 64-bit Decoder 4:1 MUX 8:1 MUX 16:1 MUX 32:1 MUX 1. These timing numbers were generated using the ispLEVER 8.0 design tool. Exact performance may vary with device and tool version. The tool uses internal parameters that have been characterized but are not tested on every device ...

  • Page 70

    ... Lattice Semiconductor Register-to-Register Performance (Continued) Function 36x36 Multiplier (All Registers) 18x18 Multiplier/Accumulate (Input and Output Registers) 18x18 Multiplier-Add/Sub-Sum (All Reg- isters) DSP IP Functions 16-Tap Fully-Parallel FIR Filter 1024-pt, Radix 4, Decimation in  Frequency FFT 8x8 Matrix Multiplier Derating Timing Tables Logic timing provided in the following sections of this data sheet and the Diamond/ispLEVER design tools are worst case numbers in the operating range ...

  • Page 71

    ... Lattice Semiconductor LatticeECP2/M External Switching Characteristics Parameter Description General I/O Pin Parameters (using Primary Clock without PLL) Clock to Output - PIO Output  Register Clock to Data Setup - PIO Input t SU Register Clock to Data Hold - PIO Input  Register Over Recommended Operating Conditions ...

  • Page 72

    ... Lattice Semiconductor LatticeECP2/M External Switching Characteristics Parameter Description Clock to Data Setup - PIO Input t SU_DEL Register with Data Input Delay Clock to Data Hold - PIO Input Reg- t H_DEL ister with Input Data Delay Clock Frequency of I/O Register and f MAX_IO PFU Register General I/O Pin Parameters (using Edge Clock without PLL) ...

  • Page 73

    ... Lattice Semiconductor LatticeECP2/M External Switching Characteristics Parameter Description Clock to Data Setup - PIO Input t SUE Register Clock to Data Hold - PIO Input t HE Register Clock to Data Setup - PIO Input t SU_DELE Register with Data Input Delay Over Recommended Operating Conditions -7 Device Min. LFE2-6 0.00 LFE2-12 0 ...

  • Page 74

    ... Lattice Semiconductor LatticeECP2/M External Switching Characteristics Parameter Description Clock to Data Hold - PIO Input t H_DELE Register with Input Data Delay Clock Frequency of I/O and PFU f MAX_IOE Register General I/O Pin Parameters (using Primary Clock with PLL) Clock to Output - PIO Output 10 t COPLL ...

  • Page 75

    ... Lattice Semiconductor LatticeECP2/M External Switching Characteristics Parameter Description Clock to Data Hold - PIO Input t HPLL Register Clock to Data Setup - PIO Input t SU_DELPLL Register with Data Input Delay Clock to Data Hold - PIO Input  t H_DELPLL Register with Input Data Delay 2 DDR I/O Pin Parameters ...

  • Page 76

    ... Lattice Semiconductor LatticeECP2/M External Switching Characteristics Parameter Description t Data Valid Before DQS (DDR Write) ECP2/M DQVBS t Data Valid After DQS (DDR Write) DQVAS f DDR Clock Frequency MAX_DDR2 SPI4.2 I/O Pin Parameters Static Alignment Maximum Data Rate t Data Valid After CLK (Receive) ...

  • Page 77

    ... Lattice Semiconductor LatticeECP2/M External Switching Characteristics Parameter Description t Data Invalid Before Clock (Transmit) DIBSPI XGMII I/O Pin Parameters (312 Mbps) t Data Setup Before Read Clock SUXGMII t Data Hold After Read Clock HXGMII t Data Valid Before Clock DVBCKXGMII t Data Valid After Clock ...

  • Page 78

    ... Lattice Semiconductor Figure 3-6. SPI4.2 Parameters t DIBSPI CLK Data (TDAT, TCTL) t DIASPI RDTCLK Data (RDAT,RCTL) t DVACLKSPI Transmit Parameters t DIASPI t DIBSPI Receiver Parameters t DVACLKSPI t t DVECLKSPI DVECLKSPI 3-26 DC and Switching Characteristics LatticeECP2/M Family Data Sheet ...

  • Page 79

    ... Lattice Semiconductor Figure 3-7. DDR and DDR2 Parameters DQS DQ t DQVBS t DQVAS DQS DQ t DVADQ Figure 3-8. XGMII Parameters CLOCK DATA t DVBCKXGMII t DVACKXGMII CLOCK DATA t SUXGMII t HXGMII Transmit Parameters t DQVAS t DQVBS Receiver Parameters t DVADQ t t DVEDQ DVEDQ Transmit Parameters t DVACKXGMII t DVBCKXGMII ...

  • Page 80

    ... Lattice Semiconductor LatticeECP2/M Internal Switching Characteristics Parameter Description PFU/PFF Logic Mode Timing t LUT4 delay ( inputs to F output) LUT4_PFU t LUT6 delay ( inputs to OFX output) LUT6_PFU Set/Reset to output of PFU (Asynchro- t LSR_PFU nous) t Clock to Mux (M0,M1) Input Setup Time SUM_PFU t Clock to Mux (M0,M1) Input Hold Time ...

  • Page 81

    ... Lattice Semiconductor LatticeECP2/M Internal Switching Characteristics Parameter Description t Hold Write/Read Enable to PFU Memory HWREN_EBR Clock Enable Setup Time to EBR Output t SUCE_EBR Register Clock Enable Hold Time to EBR Output t HCE_EBR Register Reset To Output Delay Time from EBR t RSTO_EBR Output Register Byte Enable Set-Up Time to EBR Output ...

  • Page 82

    ... Lattice Semiconductor Timing Diagrams Figure 3-9. Read/Write Mode (Normal) CLKA CSA WEA ADA DIA D0 DOA Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive edge of the clock. Figure 3-10. Read/Write Mode with Input and Output Registers ...

  • Page 83

    ... Lattice Semiconductor Figure 3-11. Write Through (SP Read/Write on Port A, Input Registers Only) CLKA CSA WEA ADA DIA Data from Prev Read DOA or Write Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive edge of the clock. ...

  • Page 84

    ... Lattice Semiconductor LatticeECP2/M Family Timing Adders Buffer Type Input Adjusters LVDS25 LVDS BLVDS25 BLVDS MLVDS LVDS RSDS RSDS LVPECL33 LVPECL HSTL18_I HSTL_18 class I HSTL18_II HSTL_18 class II HSTL18D_I Differential HSTL 18 class I HSTL18D_II Differential HSTL 18 class II HSTL15_I HSTL_15 class I HSTL15D_I Differential HSTL 15 class I ...

  • Page 85

    ... Lattice Semiconductor LatticeECP2/M Family Timing Adders Buffer Type HSTL15_I HSTL_15 class I 4mA drive HSTL15D_I Differential HSTL 15 class I 4mA drive SSTL33_I SSTL_3 class I SSTL33_II SSTL_3 class II SSTL33D_I Differential SSTL_3 class I SSTL33D_II Differential SSTL_3 class II SSTL25_I SSTL_2 class I 8mA drive SSTL25_II SSTL_2 class II 16mA drive ...

  • Page 86

    ... Lattice Semiconductor LatticeECP2/M Family Timing Adders Buffer Type LVCMOS25_4mA LVCMOS 2.5 4mA drive, slow slew rate LVCMOS25_8mA LVCMOS 2.5 8mA drive, slow slew rate LVCMOS25_12mA LVCMOS 2.5 12mA drive, slow slew rate LVCMOS25_16mA LVCMOS 2.5 16mA drive, slow slew rate LVCMOS25_20mA LVCMOS 2 ...

  • Page 87

    ... Lattice Semiconductor sysCLOCK GPLL Timing Parameter Description f Input Clock Frequency (CLKI, CLKFB) IN Output Clock Frequency (CLKOP, f OUT CLKOS) f K-Divider Output Frequency (CLKOK) OUT2 f PLL VCO Frequency VCO f Phase Detector Input Frequency PFD AC Characteristics t Output Clock Duty Cycle Output Phase Accuracy Output Clock Period Jitter ...

  • Page 88

    ... Lattice Semiconductor sysCLOCK SPLL Timing Parameter Description f Input Clock Frequency (CLKI, CLKFB Output Clock Frequency (CLKOP, CLKOS) OUT f K-Divider Output Frequency (CLKOK) OUT2 f PLL VCO Frequency VCO f Phase Detector Input Frequency PFD AC Characteristics t Output Clock Duty Cycle Output Phase Accuracy Output Clock Period Jitter ...

  • Page 89

    ... Lattice Semiconductor DLL Timing Parameter f Input reference clock frequency (on-chip or off-chip) REF f Feedback clock frequency (on-chip or off-chip Output clock frequency, CLKOP CLKOP 2 f Output clock frequency, CLKOS CLKOS t Output clock period jitter (clean input) PJIT t Output clock cycle to cycle jitter (clean input) ...

  • Page 90

    ... Lattice Semiconductor SERDES High-Speed Data Transmitter (LatticeECP2M Family Only) Table 3-7. Serial Output Timing and Levels Symbol Description Differential swing (1V setting) V TX-DIFF-P-P-1 Differential swing (1.25V setting) V TX-DIFF-P-P-1.25 Differential swing (1.3V setting) V TX-DIFF-P-P-1.3 Differential swing (1.35V setting) V TX-DIFF-P-P-1.35 Output common mode voltage ...

  • Page 91

    ... Lattice Semiconductor Table 3-9. Channel Output Jitter - x20 Mode Description Frequency Deterministic 3.125 Gbps Random 3.125 Gbps Total 3.125 Gbps Deterministic 2.5 Gbps Random 2.5 Gbps Total 2.5 Gbps Deterministic 1.25 Gbps Random 1.25 Gbps Total 1.25 Gbps Note: Values are measured with PRBS 2 x20 mode ...

  • Page 92

    ... Lattice Semiconductor Figure 3-12. Transmitter and Receiver Block Diagram SERDES REFCLK HDINPi EQ CDR HDINNi Receiver Transmit Clock REFCLK TX PLL T4 HDOUTPi Serializer 8:1/10:1 HDOUTNi Transmitter SERDES Bridge Recovered Clock Deserializer Polarity 1:8/1:10 Adjust BYPASS BYPASS T3 Encoder Polarity Adjust BYPASS BYPASS 3-40 DC and Switching Characteristics ...

  • Page 93

    ... Lattice Semiconductor SERDES High Speed Data Receiver (LatticeECP2M Family Only) Table 3-11. Serial Input Data Specifications Symbol Description Stream of nontransitions RX-CID S (CID = Consecutive Identical Digits Differential input sensitivity RX-DIFF-S V Input levels RX-IN V Input common mode range (DC coupled) RX-CM-DC V Input common mode range (AC coupled) ...

  • Page 94

    ... Lattice Semiconductor Table 3-13. Periodic Receiver Jitter Tolerance Specification Description Frequency 3.125 Gbps 600 mV differential eye 2.5 Gbps 600 mV differential eye Periodic 1.25 Gbps 600 mV differential eye 2 250 Mbps 600 mV differential eye 7 1. Values are measured with PRBS 2 -1, all channels operating. ...

  • Page 95

    ... Lattice Semiconductor SERDES External Reference Clock (LatticeECP2M Family Only) The external reference clock selection and its interface are a critical part of system applications for this product. Table 3-14 specifies reference clock requirements, over the full range of operating conditions. Table 3-14. External Reference Clock Specification (refclkp/refclkn) ...

  • Page 96

    ... Lattice Semiconductor PCI Express Electrical and Timing Characteristics AC and DC Characteristics 1, 2 Table 3-16. Transmit Symbol UI Unit interval Differential peak-to-peak output V TX-DIFF_P-P voltage De-emphasis differential output V TX-DE-RATIO voltage ratio RMS AC peak common-mode out- V TX-CM-AC_P put voltage Maximum Common mode voltage V TX-CM-DC-LINE-DELTA delta between n and p channels ...

  • Page 97

    ... Lattice Semiconductor Table 3-18. Reference Clock Symbol F Reference clock frequency REFCLK V Input common mode voltage Clock input rise/fall time Differential input voltage swing SW DC Input clock duty cycle REFCLK PPM Reference clock tolerance Description Test Conditions 3-45 DC and Switching Characteristics LatticeECP2/M Family Data Sheet Min ...

  • Page 98

    ... Lattice Semiconductor LatticeECP2/M sysCONFIG Port Timing Specifications Parameter sysCONFIG Byte Data Flow t Byte D[0:7] Setup Time to CCLK SUCBDI t Byte D[0:7] Hold Time to CCLK HCBDI t CCLK to DOUT in Flowthrough Mode CODO t CSN[0:1] Setup Time to CCLK SUCS t CSN[0:1] Hold Time to CCLK HCS t Write Signal Setup Time to CCLK ...

  • Page 99

    ... Lattice Semiconductor LatticeECP2/M sysCONFIG Port Timing Specifications (Continued) Parameter t SOSPI Data Setup Time Before CCLK SUSPI t SOSPI Data Hold Time After CCLK HSPI 1. Re-toggling the PROGRAMN pin is not permitted until the INITN pin is high. Avoid consecutive toggling of the PROGRAMN. 2. For SED (Soft Error Detect), the SEDCLKIN operating frequency must be at least 20MHz. SEDCLKIN is derived from Master Clock Fre- quency that has a +/-30% variation ...

  • Page 100

    ... Lattice Semiconductor Figure 3-15. sysCONFIG Parallel Port Write Cycle 1 CCLK CS1N CSN WRITEN BUSY D[0: Master Parallel Mode the FPGA provides CCLK. In Slave Parallel Mode the external device provides CCLK. Figure 3-16. sysCONFIG Slave Serial Port Timing CCLK (input) DIN DOUT Figure 3-17 ...

  • Page 101

    ... Lattice Semiconductor Figure 3-18. Configuration from PROGRAMN Timing PROGRAMN t DPPINIT INITN t DINITD DONE CCLK CFG[2:0] USER I/O 1. The CFG pins are normally static (hard wired) Figure 3-19. Wake-Up Timing PROGRAMN INITN DONE CCLK USER I/O Figure 3-20. SPI/SPIm Configuration Waveforms Capture ...

  • Page 102

    ... Lattice Semiconductor JTAG Port Timing Specifications Symbol f TCK clock frequency MAX t TCK [BSCAN] clock pulse width BTCP t TCK [BSCAN] clock pulse width high BTCPH t TCK [BSCAN] clock pulse width low BTCPL t TCK [BSCAN] setup time BTS t TCK [BSCAN] hold time BTH ...

  • Page 103

    ... Lattice Semiconductor Switching Test Conditions Figure 3-22 shows the output test load that is used for AC testing. The specific values for resistance, capacitance, voltage, and other test conditions are shown in Table 3-19. Figure 3-22. Output Test Load, LVTTL and LVCMOS Standards Table 3-19. Test Fixture Required Components, Non-Terminated Interfaces Test Condition LVTTL and other LVCMOS settings (L -> ...

  • Page 104

    ... C]_FB_A PCLK[T, C]_[n:0]_[3:0] © 2011 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...

  • Page 105

    ... Lattice Semiconductor Signal Descriptions (Cont.) Signal Name [LOC]DQS[num] [LOC]DQ[num] Test and Programming (Dedicated Pins) TMS TCK TDI TDO VCCJ Configuration Pads (Used During sysCONFIG) CFG[2:0] INITN PROGRAMN DONE CCLK BUSY/SISPI CSN CS1N WRITEN D[0]/SPIFASTN D[1:6] D[7]/SPID0 DOUT/CSON DI/CSSPI0N Dedicated SERDES Signals ...

  • Page 106

    ... Lattice Semiconductor Signal Descriptions (Cont.) Signal Name [LOC]_SQ_VCCIBm [LOC]_SQ_VCCOBm [LOC]_SQ_HDOUTNm [LOC]_SQ_HDOUTPm [LOC]_SQ_HDINNm [LOC]_SQ_HDINPm 4 [LOC]_SQ_VCCTXm 4 [LOC]_SQ_VCCRXm 1. These signals are relevant for LatticeECP2M family defines the associated channel in the Quad. 3. These signals are defined in Quads [LOC] indicates the corner SERDES Quad is located: ULC (upper left), URC (upper right), LLC (lower left), LRC (lower right) ...

  • Page 107

    ... Lattice Semiconductor PICs and DDR Data (DQ) Pins Associated with the DDR Strobe (DQS) Pin PICs Associated with DQS Strobe For Left and Right Edges of the Device P[Edge] [n-4] P[Edge] [n-3] P[Edge] [n-2] P[Edge] [n-1] P[Edge] [n] P[Edge] [n+1] P[Edge] [n+2] P[Edge] [n+3] ...

  • Page 108

    ... Lattice Semiconductor LatticeECP2 Pin Information Summary, LFE2-6 and LFE2-12 Pin Type Single Ended User I/O Differential Pair User I/O TAP Pins Configuration Muxed Pins Dedicated Pins (Non TAP) Muxed Pins Non Configuration Dedicated Pins VCC VCCAUX VCCPLL Bank0 Bank1 Bank2 Bank3 ...

  • Page 109

    ... Lattice Semiconductor LatticeECP2 Pin Information Summary, LFE2-6 and LFE2-12 (Cont.) Pin Type Bank0 Bank1 Bank2 Bank3 Available DDR-Interfaces per I/O Bank4 1 Bank Bank5 Bank6 Bank7 Bank8 Bank0 Bank1 Bank2 Bank3 PCI Capable I/Os per Bank Bank4 Bank5 Bank6 Bank7 Bank8 1. Minimum requirement to implement a fully functional 8-bit wide DDR bus. Available DDR interface consists of at least 12 I/Os (1 DQS + 1 DQSB + 8 DQs + Bank VREF1) ...

  • Page 110

    ... Lattice Semiconductor LatticeECP2 Pin Information Summary, LFE2-20 and LFE2-35 Pin Type Single Ended User I/O Differential Pair User I/O TAP Pins Configuration Muxed Pins Dedicated Pins (Non TAP) Muxed Pins Non Configuration Dedicated Pins VCC VCCAUX VCCPLL Bank0 Bank1 Bank2 Bank3 ...

  • Page 111

    ... Lattice Semiconductor LatticeECP2 Pin Information Summary, LFE2-20 and LFE2-35 (Cont.) Pin Type Bank0 Bank1 Bank2 Bank3 Available DDR-Interfaces per I/O Bank4 1 Bank Bank5 Bank6 Bank7 Bank8 Bank0 Bank1 Bank2 Bank3 PCI Capable I/Os per Bank Bank4 Bank5 Bank6 Bank7 Bank8 1. Minimum requirement to implement a fully functional 8-bit wide DDR bus. Available DDR interface consists of at least 12 I/Os (1 DQS + 1 DQSB + 8 DQs + Bank VREF1) ...

  • Page 112

    ... Lattice Semiconductor LatticeECP2 Pin Information Summary, LFE2-50 and LFE2-70 Pin Type Single Ended User I/O Differential Pair User I/O TAP Pins Configuration Muxed Pins Dedicated Pins (Non TAP) Muxed Pins Non Configuration Dedicated Pins VCC VCCAUX VCCPLL Bank0 Bank1 Bank2 Bank3 ...

  • Page 113

    ... Lattice Semiconductor LatticeECP2 Pin Information Summary, LFE2-50 and LFE2-70 (Cont.) Pin Type Bank0 Bank1 Bank2 Bank3 Available DDR-Interfaces per I/O Bank4 1 Bank Bank5 Bank6 Bank7 Bank8 Bank0 Bank1 Bank2 Bank3 PCI Capable I/Os per Bank Bank4 Bank5 Bank6 Bank7 Bank8 1. Minimum requirement to implement a fully functional 8-bit wide DDR bus. Available DDR interface consists of at least 12 I/Os (1 DQS + 1 DQSB + 8 DQs + Bank VREF1) ...

  • Page 114

    ... Lattice Semiconductor LatticeECP2M Pin Information Summary, LFE2M20 and LFE2M35 Pin Type Single Ended User I/O Differential Pair User I/O TAP Pins Configuration Muxed Pins Dedicated Pins (Non TAP) Muxed Pins Non Configuration Dedicated Pins VCC VCCAUX VCCPLL Bank0 Bank1 Bank2 Bank3 ...

  • Page 115

    ... Lattice Semiconductor LatticeECP2M Pin Information Summary, LFE2M20 and LFE2M35 (Cont.) Pin Type Bank0 Bank1 Bank2 Bank3 Available DDR-Interfaces per Bank4 1 I/O Bank Bank5 Bank6 Bank7 Bank8 Bank0 Bank1 Bank2 Bank3 PCI Capable I/Os per Bank Bank4 Bank5 Bank6 Bank7 Bank8 1. Minimum requirement to implement a fully functional 8-bit wide DDR bus. Available DDR interface consists of at least 12 I/Os (1 DQS + 1 DQSB + 8 DQs + Bank VREF1) ...

  • Page 116

    ... Lattice Semiconductor LatticeECP2M Pin Information Summary, LFE2M50, LFE2M70 and LFE2M100 Pin Type Single Ended User I/O Differential Pair User I/O TAP Pins Muxed Pins Configuration Dedicated Pins (Non TAP) Muxed Pins Non Configuration Dedicated Pins VCC VCCAUX VCCPLL Bank0 Bank1 Bank2 ...

  • Page 117

    ... Lattice Semiconductor LatticeECP2M Pin Information Summary, LFE2M50, LFE2M70 and LFE2M100 (Cont.) Pin Type Bank0 Bank1 Bank2 Bank3 Available DDR-Interfaces Bank4 1 per I/O Bank Bank5 Bank6 Bank7 Bank8 Bank0 Bank1 Bank2 Bank3 PCI Capable I/Os per Bank Bank4 Bank5 Bank6 Bank7 Bank8 1 ...

  • Page 118

    ... Lattice Semiconductor Available Device Resources by Package, LatticeECP2 Resource Device ECP2-6 ECP2-12 ECP2-20 PLL/DLL ECP2-35 ECP2-50 ECP2-70 Available Device Resources by Package, LatticeECP2M Resource Device ECP2M20 ECP2M35 PLL/DLL ECP2M50 ECP2M70 ECP2M100 256 fpBGA 484 fpBGA 4 — — 4 — 6 — — 256 fpBGA 484 fpBGA ...

  • Page 119

    ... Lattice Semiconductor LatticeECP2 Power Supply and NC 3 Signals 144 TQFP VCC 16, 22, 29, 48, 54, 83, 94, 102, 128, 135 VCCIO0 139 VCCIO1 117 VCCIO2 106 VCCIO3 89 VCCIO4 64 VCCIO5 42 VCCIO6 31 VCCIO7 9 VCCIO8 85 VCCJ 35 VCCAUX 6, 39, 90, 142 VCCPLL None 1 GND 11, 21, 30, 47, 51, 61, 81, 95, 105, 120, 133, ...

  • Page 120

    ... Lattice Semiconductor LatticeECP2 Power Supply and NC (Cont.) Signals VCC LFE2-20: R8, P18, M8, L20, L12, L13, L14, L15, M11, M12, M15, M16, N11, N16, P11, P16, R11, R12, R15, R16, T12, T13, T14, T15 LFE2-35/LFE2-50: L12, L13, L14, L15, M11, M12, M15, M16, N11, N16, P11, P16, R11, R12, R15, ...

  • Page 121

    ... Lattice Semiconductor LatticeECP2M Power Supply and NC Signal V G7, G9, H7, J10, K10 CCIO0 V E10 CCIO1 V E14, G12 CCIO2 V K12, M14 CCIO3 V M10, P12 CCIO4 V M7, P5 CCIO5 V K5, M3 CCIO6 V E3, G5 CCIO7 V T15 CCIO8 V K7 CCJ V G8, H10, J7, K9 CCAUX V G10 CCPLL 3 SERDES Power ...

  • Page 122

    ... Lattice Semiconductor LatticeECP2M Power Supply and NC (Cont.) Signal V LFE2M35: AD13, AD14, AD16, AD17, AD19, AD21, CC AD22, AD24, AD25, L12, L13, L14, L15, M11, M12, M15, M16, N11, N16, P11, P16, R11, R12, R15, R16, T12, T13, T14, T15 LFE2M50: L12, L13, L14, L15, M11, M12, M15, M16, ...

  • Page 123

    ... Lattice Semiconductor LatticeECP2M Power Supply and NC (Cont.) Signal 1 GND A13, A19, A2, A25, AA2, AA25, AB18, AB22, AB5, AB9, AE1, AE11, AE16, AE22, AE26, AE6, AF13, AF19, AF2, AF25, B1, B11, B16, B22, B26, B6, E18, E22, E5, E9, F2, F25, G11, G16, J22, J5, K11, K13, ...

  • Page 124

    ... Lattice Semiconductor LatticeECP2M Power Supply and NC (Cont.) Signal V AA13, AA14, AA15, AA16, AA17, AA18, AA19, AA20, AA21, AA22, AB14, AB15, AB20, AB21, N14, N15, N20, N21, CC P13, P14, P15, P16, P17, P18, P19, P20, P21, P22, R13, R14, R21, R22, T14, T21, U14, U21, V14, V21, W14, W21, ...

  • Page 125

    ... Lattice Semiconductor LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 144 TQFP LFE2-6E/SE Pin Pin/Pad Number Function Bank 1 PL2A 7 2 PL2B 7 3 PL4A 7 4 PL4B 7 5 PL6A 7 6 VCCAUX - 7 PL6B 7 8 PL8A 7 9 VCCIO7 7 10 PL8B 7 11 GND - 12 PL12A 7 13 PL12B 7 14 PL13A ...

  • Page 126

    ... Lattice Semiconductor LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 144 TQFP (Cont.) LFE2-6E/SE Pin Pin/Pad Number Function Bank GND - 48 VCC 49 PB8A 5 50 PB8B 5 51 GND - 52 PB13A 4 PCLKT4_0/BDQ15 53 PB13B 4 PCLKC4_0/BDQ15 54 VCC - 55 PB14A 4 56 PB14B 4 57 PB16A 4 58 PB16B 4 59 PB18A 4 60 PB18B 4 61 ...

  • Page 127

    ... Lattice Semiconductor LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 144 TQFP (Cont.) LFE2-6E/SE Pin Pin/Pad Number Function Bank 91 PR20B 3 RLM0_GPLLC_IN_A** 92 PR20A 3 RLM0_GPLLT_IN_A** 93 RLM0_PLLCAP 3 94 VCC - 95 GND - 96 PR17B 3 RLM0_GDLLC_IN_A** 97 PR17A 3 RLM0_GDLLT_IN_A** 98 PR16B 3 99 PR16A 3 100 PR15B 3 101 PR15A 3 102 VCC - 103 PR13B 2 104 ...

  • Page 128

    ... Lattice Semiconductor LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 144 TQFP (Cont.) LFE2-6E/SE Pin Pin/Pad Number Function Bank 136 PT6B 0 137 PT6A 0 138 GND - 139 VCCIO0 0 140 PT4B 0 141 PT4A 0 142 VCCAUX - 143 PT2B 0 144 PT2A 0 * Supports true LVDS. Other differential signals must be emulated with external resistors. ...

  • Page 129

    ... Lattice Semiconductor LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 208 PQFP LFE2-12E/SE Pin Pin/Pad Number Function Bank Function 1 PL2A 7 VREF2_7 2 PL2B 7 VREF1_7 3 PL4A 7 4 PL4B 7 5 GND - 6 PL6A 7 7 VCCAUX - 8 PL6B 7 9 PL8A 7 10 VCCIO7 7 11 PL8B 7 12 VCC - 13 GND - 14 VCCIO7 7 15 ...

  • Page 130

    ... Lattice Semiconductor LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 208 PQFP (Cont.) LFE2-12E/SE Pin Pin/Pad Number Function Bank 46 PL28B 6 47 PL30A 6 48 TCK - 49 TDI - 50 TDO - 51 VCCJ - 52 TMS - 53 PB2A 5 VREF2_5/BDQ6 54 PB2B 5 VREF1_5/BDQ6 55 VCCIO5 5 56 PB6A 5 57 PB6B 5 58 PB8A 5 59 PB8B 5 60 GND ...

  • Page 131

    ... Lattice Semiconductor LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 208 PQFP (Cont.) LFE2-12E/SE Pin Pin/Pad Number Function Bank Function 92 PB44A 4 93 VCCIO4 4 94 PB44B 4 95 PB48A 4 96 PB48B 4 97 VCC - 98 PB52A 4 99 PB52B 4 100 VCCIO4 4 101 PB54A 4 102 GND - 103 PB55A 4 VREF2_4/BDQ51 ...

  • Page 132

    ... Lattice Semiconductor LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 208 PQFP (Cont.) LFE2-12E/SE Pin Pin/Pad Number Function Bank Function 138 PR15A 3 PCLKT3_0 139 GND - 140 VCC - 141 PR13B 2 PCLKC2_0/RDQ10 142 PR13A 2 PCLKT2_0/RDQ10 143 VCCIO2 2 144 PR12A 2 145 GND - 146 VCC - 147 PR8B ...

  • Page 133

    ... Lattice Semiconductor LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 208 PQFP (Cont.) LFE2-12E/SE Pin Pin/Pad Number Function Bank Function 184 GND - 185 PT28A 0 PCLKT0_0 186 PT26B 0 187 PT26A 0 188 VCC - 189 PT20B 0 190 VCCAUX - 191 PT20A 0 192 GND - 193 PT18B 0 194 PT18A ...

  • Page 134

    ... Lattice Semiconductor LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 256 fpBGA LFE2-6E/SE Ball Ball/Pad Number Function Bank Dual Function C3 PL2A 7 C2 PL2B 7 VCCIO VCCIO7 PL5A 7 D4 PL4A 7 D2 PL5B 7 GND GNDIO7 - E4 PL4B 7 B1 PL7A 7 C1 PL7B 7 F5 PL9A 7 VCCIO VCCIO7 7 F4 PL8A ...

  • Page 135

    ... Lattice Semiconductor LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 256 fpBGA (Cont.) LFE2-6E/SE Ball Ball/Pad Number Function Bank Dual Function GND GNDIO6 - L2 PL24A 6 K2 PL25A 6 L3 PL24B 6 K1 PL25B 6 VCCIO VCCIO6 6 L4 PL26A 6 L1 PL27A 6 L5 PL26B 6 M1 PL27B 6 GND GNDIO6 - N1 PL29A ...

  • Page 136

    ... Lattice Semiconductor LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 256 fpBGA (Cont.) LFE2-6E/SE Ball Ball/Pad Number Function Bank Dual Function M8 PB8B 5 PCLKC5_0/BDQ6 GND GNDIO5 - P7 PB13A 4 PCLKT4_0/BDQ15 R8 PB13B 4 PCLKC4_0/BDQ15 VCCIO VCCIO4 4 T5 PB14A 4 T6 PB14B 4 T8 PB15A 4 GND GNDIO4 - R7 PB16A 4 T9 PB15B 4 T7 ...

  • Page 137

    ... Lattice Semiconductor LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 256 fpBGA (Cont.) LFE2-6E/SE Ball Ball/Pad Number Function Bank Dual Function N14 CFG1 8 N13 PROGRAMN 8 N15 CFG0 8 P15 PR30B 8 L12 INITN 8 N16 PR29B 8 GND GNDIO8 - R14 CCLK 8 P14 PR30A 8 M13 DONE 8 R16 PR28B ...

  • Page 138

    ... Lattice Semiconductor LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 256 fpBGA (Cont.) LFE2-6E/SE Ball Ball/Pad Number Function Bank Dual Function F15 PR11B 2 G11 PR12B 2 F14 PR11A 2 VCCIO VCCIO2 2 F12 PR12A 2 G14 PR10B 2 G13 PR10A 2 GND GNDIO2 - F16 PR8B 2 F9 PR9B 2 E16 PR8A ...

  • Page 139

    ... Lattice Semiconductor LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 256 fpBGA (Cont.) LFE2-6E/SE Ball Ball/Pad Number Function Bank Dual Function - - - - - - D10 PT19B 1 C10 PT19A 1 GND GNDIO1 - B10 PT18B 1 A9 PT17B 1 A10 PT18A 1 B9 PT17A 1 VCCIO VCCIO1 1 A8 PT16B 1 D9 PT15B 1 B8 PT16A ...

  • Page 140

    ... Lattice Semiconductor LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 256 fpBGA (Cont.) LFE2-6E/SE Ball Ball/Pad Number Function Bank Dual Function D5 PT2B 0 E5 PT2A 0 G7 VCC - G9 VCC - H7 VCC - J10 VCC - K10 VCC - K8 VCC - G8 VCCAUX - H10 VCCAUX - J7 VCCAUX - K9 VCCAUX - C5 VCCIO0 0 E7 VCCIO0 0 C12 VCCIO1 ...

  • Page 141

    ... Lattice Semiconductor LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 256 fpBGA (Cont.) LFE2-6E/SE Ball Ball/Pad Number Function Bank Dual Function R12 GND - R5 GND - T1 GND - T16 GND - * Supports true LVDS. Other differential signals must be emulated with external resistors. ** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant. ...

  • Page 142

    ... Lattice Semiconductor LFE2-20E/SE Logic Signal Connections: 256 fpBGA Ball Number Ball Number VCCIO VCCIO GND - GND GND VCC VCCIO GND GND VCCIO VCCIO GND GND VCCIO VCCIO GND GND G10 G10 GND GND LFE2-20E/SE Ball/Pad Function Bank PL2A 7 PL2B 7 VCCIO7 7 GNDIO7 ...

  • Page 143

    ... Lattice Semiconductor LFE2-20E/SE Logic Signal Connections: 256 fpBGA (Cont.) Ball Number Ball Number VCCIO VCCIO J2 J2 GND GND VCCIO VCCIO GND GND VCCIO VCCIO GND GND VCC - GND - VCCIO VCCIO LFE2-20E/SE Ball/Pad Function Bank PL31A 6 PL30B 6 VCCIO6 6 PL31B 6 GNDIO6 - PL38A 6 PL39A ...

  • Page 144

    ... Lattice Semiconductor LFE2-20E/SE Logic Signal Connections: 256 fpBGA (Cont.) Ball Number Ball Number GND GND VCCIO VCCIO M8 M8 GND GND VCCIO VCCIO GND GND VCCIO VCCIO GND GND R10 R10 VCC - GND - N9 N9 T10 T10 M9 M9 R11 R11 P10 P10 N11 ...

  • Page 145

    ... Lattice Semiconductor LFE2-20E/SE Logic Signal Connections: 256 fpBGA (Cont.) Ball Number Ball Number L11 L11 T13 T13 R13 R13 VCCIO VCCIO T14 T14 P13 P13 GND GND N12 N12 M12 M12 R15 R15 N14 N14 N13 N13 N15 N15 P15 P15 ...

  • Page 146

    ... Lattice Semiconductor LFE2-20E/SE Logic Signal Connections: 256 fpBGA (Cont.) Ball Number Ball Number J13 J13 J12 J12 H12 H12 GND GND H13 H13 H15 H15 VCCIO VCCIO H16 H16 H11 H11 J11 J11 G16 G16 GND GND G15 G15 F15 F15 ...

  • Page 147

    ... Lattice Semiconductor LFE2-20E/SE Logic Signal Connections: 256 fpBGA (Cont.) Ball Number Ball Number VCCIO VCCIO D12 D12 B14 B14 C14 C14 A14 A14 D13 D13 C13 C13 GND GND A13 A13 B13 B13 VCCIO VCCIO A12 A12 B11 B11 D11 D11 ...

  • Page 148

    ... Lattice Semiconductor LFE2-20E/SE Logic Signal Connections: 256 fpBGA (Cont.) Ball Number Ball Number VCCIO VCCIO GND GND VCCIO VCCIO GND - VCC - J10 J10 K10 K10 H10 H10 C12 C12 E10 E10 E14 E14 G12 G12 K12 K12 M14 M14 M10 M10 ...

  • Page 149

    ... Lattice Semiconductor LFE2-20E/SE Logic Signal Connections: 256 fpBGA (Cont.) Ball Number Ball Number T15 T15 A1 A1 A16 A16 B12 B12 E15 E15 E2 E2 H14 H14 M15 M15 R12 R12 T16 T16 * Supports true LVDS. Other differential signals must be emulated with external resistors. ...

  • Page 150

    ... Lattice Semiconductor LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 484 fpBGA LFE2-12E/12SE Ball Ball/Pad Number Function Bank Dual Function E4 PL2A 7 E5 PL2B PL3A PL3B 7 VCCIO VCCIO7 7 E2 PL4A 7 G6 PL5A 7 E1 PL4B 7 G7 PL5B 7 GNDIO GNDIO7 - PL7A 7 H1 PL6A 7 J5 PL7B 7 L6 ...

  • Page 151

    ... Lattice Semiconductor LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 484 fpBGA LFE2-12E/12SE Ball Ball/Pad Number Function Bank Dual Function M3 PL16A 6 GNDIO GNDIO6 - M4 PL16B PL17A 6 LLM0_GDLLT_IN_A** P2 PL17B 6 LLM0_GDLLC_IN_A** P4 PL18A 6 LLM0_GDLLT_FB_A - - - R4 PL18B 6 LLM0_GDLLC_FB_A P6 LLM0_PLLCAP 6 R1 PL20A 6 LLM0_GPLLT_IN_A** GNDIO GNDIO6 - R3 PL21A 6 LLM0_GPLLT_FB_A R2 PL20B 6 LLM0_GPLLC_IN_A** T4 PL21B ...

  • Page 152

    ... Lattice Semiconductor LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 484 fpBGA LFE2-12E/12SE Ball Ball/Pad Number Function Bank Dual Function AA2 PL31A 6 VCCIO VCCIO6 6 Y1 PL28A 6 AA1 PL31B 6 W1 PL28B 6 V3 PL30B 6 GNDIO GNDIO6 - V4 PL30A 6 U5 TDI - U7 TCK - V6 TDO - V5 TMS - T8 VCCJ - W4 PB3A 5 Y3 ...

  • Page 153

    ... Lattice Semiconductor LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 484 fpBGA LFE2-12E/12SE Ball Ball/Pad Number Function Bank Dual Function W9 PB15A 5 AA8 PB16B 5 V9 PB15B 5 AB8 PB18A 5 VCCIO VCCIO5 5 W10 PB17A 5 AA9 PB18B 5 V10 PB17B 5 GNDIO GNDIO5 - Y10 PB21A 5 AB9 PB20A 5 AA10 PB21B ...

  • Page 154

    ... Lattice Semiconductor LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 484 fpBGA LFE2-12E/12SE Ball Ball/Pad Number Function Bank Dual Function AB18 PB39A 4 AB19 PB39B 4 Y15 PB41A 4 V14 PB40A 4 VCCIO VCCIO4 4 AA15 PB41B 4 W15 PB40B 4 GNDIO GNDIO4 - AB20 PB43A 4 AA16 PB42A 4 AB21 PB43B 4 AA17 ...

  • Page 155

    ... Lattice Semiconductor LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 484 fpBGA LFE2-12E/12SE Ball Ball/Pad Number Function Bank Dual Function V22 INITN 8 R16 PR30B 8 GNDIO GNDIO8 - W22 CCLK 8 R17 PR30A 8 V21 DONE 8 VCCIO VCCIO8 8 U19 PR29B 8 T17 PR26B 8 U20 PR29A 8 D0/SPIFASTN U21 PR28A ...

  • Page 156

    ... Lattice Semiconductor LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 484 fpBGA LFE2-12E/12SE Ball Ball/Pad Number Function Bank Dual Function M20 PR16B 3 VCCIO VCCIO3 3 L21 PR16A 3 K21 PR15B 3 PCLKC3_0 J21 PR15A 3 PCLKT3_0 M18 PR13B 2 PCLKC2_0/RDQ10 GNDIO GNDIO2 - L17 PR13A 2 PCLKT2_0/RDQ10 L19 PR12B 2 K18 ...

  • Page 157

    ... Lattice Semiconductor LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 484 fpBGA LFE2-12E/12SE Ball Ball/Pad Number Function Bank Dual Function - - - D19 PR2B 2 E19 PR2A 2 B21 PT55B 1 B22 PT55A 1 GNDIO GNDIO1 - D18 PT53B 1 C20 PT54B 1 E18 PT53A 1 C19 PT54A 1 VCCIO VCCIO1 1 D17 PT51B 1 B20 ...

  • Page 158

    ... Lattice Semiconductor LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 484 fpBGA LFE2-12E/12SE Ball Ball/Pad Number Function Bank Dual Function GNDIO GNDIO1 - C13 PT37A 1 F14 PT36A 1 A13 PT35B 1 E13 PT34B 1 VCCIO VCCIO1 1 B13 PT35A 1 D13 PT34A 1 E12 PT33B 1 GNDIO GNDIO1 - D12 PT33A 1 A12 ...

  • Page 159

    ... Lattice Semiconductor LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 484 fpBGA LFE2-12E/12SE Ball Ball/Pad Number Function Bank Dual Function D9 PT15A 0 B5 PT16A 0 GNDIO GNDIO0 - A5 PT13B 0 F9 PT14B 0 A4 PT13A 0 E9 PT14A 0 VCCIO VCCIO0 0 G8 PT11B 0 A3 PT12B 0 E8 PT11A 0 A2 PT12A 0 GNDIO ...

  • Page 160

    ... Lattice Semiconductor LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 484 fpBGA LFE2-12E/12SE Ball Ball/Pad Number Function Bank Dual Function M9 VCC - N14 VCC - N9 VCC - P10 VCC - P11 VCC - P12 VCC - P13 VCC - G10 VCCIO0 0 G9 VCCIO0 0 H9 VCCIO0 0 H8 VCCIO0 0 G11 VCCIO1 1 G12 ...

  • Page 161

    ... Lattice Semiconductor LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 484 fpBGA LFE2-12E/12SE Ball Ball/Pad Number Function Bank Dual Function F13 VCCAUX - G18 VCCAUX - G5 VCCAUX - K5 VCCAUX - M17 VCCAUX - P17 VCCAUX - R5 VCCAUX - V11 VCCAUX - V13 VCCAUX - V15 VCCAUX - V7 VCCAUX - V8 VCCAUX - A1 GND - A22 GND - AA19 ...

  • Page 162

    ... Lattice Semiconductor LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 484 fpBGA LFE2-12E/12SE Ball Ball/Pad Number Function Bank Dual Function L8 GND - M10 GND - M11 GND - M12 GND - M13 GND - M15 GND - M8 GND - N10 GND - N11 GND - N12 GND - N13 GND - N15 GND - N8 GND ...

  • Page 163

    ... Lattice Semiconductor LFE2-35E/SE and LFE2-50E/SE Logic Signal Connections: 484 fpBGA LFE2-35E/SE Ball Ball/Pad Number Function Bank Dual Function E4 PL2A 7 VREF2_7/LDQ6 E5 PL2B 7 VREF1_7/LDQ6 VCCIO VCCIO7 - GNDIO GNDIO7 - E3 PL10A 7 F3 PL10B 7 F4 PL11A 7 F5 PL11B 7 E2 PL12A 7 VCCIO VCCIO7 7 E1 PL12B 7 G6 PL13A ...

  • Page 164

    ... Lattice Semiconductor LFE2-35E/SE and LFE2-50E/SE Logic Signal Connections: 484 fpBGA LFE2-35E/SE Ball Ball/Pad Number Function Bank Dual Function L3 PL24B 7 L2 PL25A 7 PCLKT7_0/LDQ22 GNDIO GNDIO7 - L1 PL25B 7 PCLKC7_0/LDQ22 M5 PL27A 6 PCLKT6_0/LDQ31 M6 PL27B 6 PCLKC6_0/LDQ31 M3 PL28A 6 VREF2_6/LDQ31 M4 PL28B 6 VREF1_6/LDQ31 M2 PL29A 6 VCCIO VCCIO6 6 M1 PL29B 6 N1 PL30A ...

  • Page 165

    ... Lattice Semiconductor LFE2-35E/SE and LFE2-50E/SE Logic Signal Connections: 484 fpBGA LFE2-35E/SE Ball Ball/Pad Number Function Bank Dual Function Y1 PL56A 6 W1 PL56B 6 R7 PL57A 6 VCCIO VCCIO6 6 T7 PL57B 6 V4 PL58A 6 V3 PL58B 6 AA2 PL59A 6 GNDIO GNDIO6 - AA1 PL59B 6 U7 TCK - U5 TDI - V5 TMS ...

  • Page 166

    ... Lattice Semiconductor LFE2-35E/SE and LFE2-50E/SE Logic Signal Connections: 484 fpBGA LFE2-35E/SE Ball Ball/Pad Number Function Bank Dual Function V9 PB24B 5 Y8 PB25A 5 AA8 PB25B 5 W10 PB26A 5 VCCIO VCCIO5 5 V10 PB26B 5 AB8 PB27A 5 AA9 PB27B 5 GNDIO GNDIO5 - AB9 PB29A 5 AB10 PB29B 5 Y10 PB30A ...

  • Page 167

    ... Lattice Semiconductor LFE2-35E/SE and LFE2-50E/SE Logic Signal Connections: 484 fpBGA LFE2-35E/SE Ball Ball/Pad Number Function Bank Dual Function V14 PB49A 4 W15 PB49B 4 VCCIO VCCIO4 4 Y15 PB50A 4 AA15 PB50B 4 GNDIO GNDIO4 - AA16 PB51A 4 AA17 PB51B 4 AB20 PB52A 4 AB21 PB52B 4 U15 PB53A 4 U16 ...

  • Page 168

    ... Lattice Semiconductor LFE2-35E/SE and LFE2-50E/SE Logic Signal Connections: 484 fpBGA LFE2-35E/SE Ball Ball/Pad Number Function Bank Dual Function R16 PR58B 8 R17 PR58A 8 U19 PR57B 8 U20 PR57A 8 D0/SPIFASTN VCCIO VCCIO8 8 U22 PR56B 8 U21 PR56A 8 T20 PR55B 8 GNDIO GNDIO8 - T19 PR55A 8 T17 PR54B ...

  • Page 169

    ... Lattice Semiconductor LFE2-35E/SE and LFE2-50E/SE Logic Signal Connections: 484 fpBGA LFE2-35E/SE Ball Ball/Pad Number Function Bank Dual Function M18 PR25B 2 PCLKC2_0/RDQ22 L17 PR25A 2 PCLKT2_0/RDQ22 GNDIO GNDIO2 - L19 PR24B 2 L20 PR24A 2 L18 PR23B 2 K17 PR23A 2 VCCIO VCCIO2 2 K18 PR22B 2 K19 PR22A 2 G22 ...

  • Page 170

    ... Lattice Semiconductor LFE2-35E/SE and LFE2-50E/SE Logic Signal Connections: 484 fpBGA LFE2-35E/SE Ball Ball/Pad Number Function Bank Dual Function C22 PR10A 2 VCCIO VCCIO2 2 GNDIO GNDIO2 - D19 PR2B 2 VREF2_2/RDQ6 E19 PR2A 2 VREF1_2/RDQ6 B21 PT73B 1 GNDIO GNDIO1 - B22 PT73A 1 C20 PT72B 1 C19 PT72A 1 D18 ...

  • Page 171

    ... Lattice Semiconductor LFE2-35E/SE and LFE2-50E/SE Logic Signal Connections: 484 fpBGA LFE2-35E/SE Ball Ball/Pad Number Function Bank Dual Function D14 PT46B 1 C13 PT46A 1 GNDIO GNDIO1 - E14 PT45B 1 F14 PT45A 1 A13 PT44B 1 B13 PT44A 1 VCCIO VCCIO1 1 E13 PT43B 1 D13 PT43A 1 E12 PT42B 1 D12 ...

  • Page 172

    ... Lattice Semiconductor LFE2-35E/SE and LFE2-50E/SE Logic Signal Connections: 484 fpBGA LFE2-35E/SE Ball Ball/Pad Number Function Bank Dual Function F10 PT24B 0 D9 PT24A 0 GNDIO GNDIO0 - F9 PT23B 0 E9 PT23A 0 A5 PT22B 0 A4 PT22A 0 VCCIO VCCIO0 0 A3 PT21B 0 A2 PT21A 0 G8 PT20B 0 E8 PT20A ...

  • Page 173

    ... Lattice Semiconductor LFE2-35E/SE and LFE2-50E/SE Logic Signal Connections: 484 fpBGA LFE2-35E/SE Ball Ball/Pad Number Function Bank Dual Function N9 VCC - P10 VCC - P11 VCC - P12 VCC - P13 VCC - G5 VCCAUX - K5 VCCAUX - R5 VCCAUX - V7 VCCAUX - V11 VCCAUX - V8 VCCAUX - V13 VCCAUX - V15 VCCAUX - M17 VCCAUX - P17 ...

  • Page 174

    ... Lattice Semiconductor LFE2-35E/SE and LFE2-50E/SE Logic Signal Connections: 484 fpBGA LFE2-35E/SE Ball Ball/Pad Number Function Bank P8 VCCIO6 6 R8 VCCIO6 6 J8 VCCIO7 7 K7 VCCIO7 7 L7 VCCIO7 7 M7 VCCIO7 7 P15 VCCIO8 8 R15 VCCIO8 8 A22 GND - AA19 GND - AA4 GND - AB1 GND - AB22 GND ...

  • Page 175

    ... Lattice Semiconductor LFE2-35E/SE and LFE2-50E/SE Logic Signal Connections: 484 fpBGA LFE2-35E/SE Ball Ball/Pad Number Function Bank N10 GND - N11 GND - N12 GND - N13 GND - N15 GND - N8 GND - P14 GND - P20 GND - P3 GND - P9 GND - R10 GND - R11 GND - R12 GND - R13 GND ...

  • Page 176

    ... Lattice Semiconductor LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA LFE2-20E/20SE Ball Ball/Pad Number Function Bank Dual Function D2 PL2A 7 D1 PL2B 7 GND GNDIO7 - F6 PL3A 7 F5 PL3B 7 VCCIO VCCIO7 GND GNDIO7 - VCCIO VCCIO7 GND GNDIO7 - PL4A 7 J8 PL4B 7 G2 PL5A 7 G1 PL5B ...

  • Page 177

    ... Lattice Semiconductor LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA LFE2-20E/20SE Ball Ball/Pad Number Function Bank VCCIO VCCIO7 GND GNDIO7 - M8 VCC - VCCIO VCCIO7 7 GND GNDIO7 - N1 PL12A 7 L8 PL13A 7 K8 PL13B 7 VCCIO VCCIO7 7 L6 PL14A 7 K5 PL14B 7 L7 PL15A 7 L5 PL15B 7 GND ...

  • Page 178

    ... Lattice Semiconductor LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA LFE2-20E/20SE Ball Ball/Pad Number Function Bank Dual Function GND GNDIO6 - VCCIO VCCIO6 GND GNDIO6 - R6 PL25A 6 R7 PL25B 6 W1 PL26A 6 VCCIO VCCIO6 6 Y2 PL26B 6 Y1 PL27A 6 LLM0_GDLLT_IN_A**/LDQ25 AA2 PL27B 6 LLM0_GDLLC_IN_A**/LDQ25 ...

  • Page 179

    ... Lattice Semiconductor LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA LFE2-20E/20SE Ball Ball/Pad Number Function Bank Dual Function VCCIO VCCIO6 6 Y6 PL40A 6 Y5 PL40B 6 AE2 PL41A 6 AD2 PL41B 6 GND GNDIO6 - AB3 PL42A 6 AB2 PL42B 6 W7 PL43A 6 VCCIO VCCIO6 6 W8 PL43B 6 Y7 ...

  • Page 180

    ... Lattice Semiconductor LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA LFE2-20E/20SE Ball Ball/Pad Number Function Bank AA10 PB12B 5 AC8 PB13A 5 AD8 PB13B 5 VCCIO VCCIO5 5 AB8 PB14A 5 AB10 PB14B 5 GND GNDIO5 - AE6 PB15A 5 AF6 PB15B 5 AA11 PB16A 5 AC9 PB16B 5 AB9 PB17A 5 AD9 ...

  • Page 181

    ... Lattice Semiconductor LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA LFE2-20E/20SE Ball Ball/Pad Number Function Bank Dual Function VCCIO VCCIO5 5 Y14 PB32A 5 AB14 PB32B 5 GND GNDIO5 - AE11 PB33A 5 AF11 PB33B 5 AD14 PB34A 5 AA15 PB34B 5 AE12 PB35A 5 PCLKT5_0/BDQ33 AF12 PB35B 5 PCLKC5_0/BDQ33 VCCIO ...

  • Page 182

    ... Lattice Semiconductor LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA LFE2-20E/20SE Ball Ball/Pad Number Function Bank Dual Function W16 PB54A 4 AA17 PB54B 4 AF18 PB55A 4 AF19 PB55B 4 GND GNDIO4 - AA19 NC - W17 NC - Y19 NC - Y17 NC - AF20 NC - VCCIO VCCIO4 4 AE20 NC - AA20 NC - W18 NC - AD20 NC - GND GNDIO4 ...

  • Page 183

    ... Lattice Semiconductor LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA LFE2-20E/20SE Ball Ball/Pad Number Function Bank Dual Function AA22 CCLK 8 AB24 INITN 8 AD25 DONE 8 GND GNDIO8 - W21 PR44B 8 Y22 PR44A 8 AC25 PR43B 8 AB25 PR43A 8 D0/SPIFASTN VCCIO VCCIO8 8 AD26 PR42B 8 AC26 PR42A ...

  • Page 184

    ... Lattice Semiconductor LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA LFE2-20E/20SE Ball Ball/Pad Number Function Bank Dual Function T26 PR27A 3 RLM0_GDLLT_IN_A**/RDQ25 T20 PR26B 3 T22 PR26A 3 VCCIO VCCIO3 3 R26 PR25B 3 R25 PR25A 3 R22 NC - GND GNDIO3 - T21 NC - P26 NC - P25 NC - R24 NC - VCCIO VCCIO3 ...

  • Page 185

    ... Lattice Semiconductor LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA LFE2-20E/20SE Ball Ball/Pad Number Function Bank Dual Function GND GNDIO2 - M19 PR15A 2 L22 PR14B 2 M22 PR14A 2 K21 PR13B 2 VCCIO VCCIO2 2 M21 PR13A 2 K24 PR12B 2 J24 PR12A 2 GND GNDIO2 - VCCIO VCCIO2 2 L20 ...

  • Page 186

    ... Lattice Semiconductor LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA LFE2-20E/20SE Ball Ball/Pad Number Function Bank Dual Function D25 NC - C25 NC - D24 NC - B25 NC - VCCIO VCCIO2 2 H21 NC - G22 NC - B24 NC - GND GNDIO2 - C24 NC - D23 NC - C23 NC - G21 PR3B 2 VCCIO VCCIO2 2 H20 PR3A 2 GND GNDIO2 - E22 ...

  • Page 187

    ... Lattice Semiconductor LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA LFE2-20E/20SE Ball Ball/Pad Number Function Bank Dual Function B19 NC - GND GNDIO1 - G17 NC - E18 NC - G19 NC - F17 NC - VCCIO VCCIO1 1 A20 NC - A19 NC - E17 NC - D18 NC - B18 PT55B 1 GND GNDIO1 - A18 PT55A 1 E16 PT54B 1 G16 PT54A ...

  • Page 188

    ... Lattice Semiconductor LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA LFE2-20E/20SE Ball Ball/Pad Number Function Bank Dual Function E14 PT41A 1 A12 PT40B 1 B12 PT40A 1 VCCIO VCCIO1 1 F14 PT39B 1 D14 PT39A 1 H16 XRES 1 H14 PT37B 0 GND GNDIO0 - H13 PT37A 0 A11 PT36B 0 B11 ...

  • Page 189

    ... Lattice Semiconductor LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA LFE2-20E/20SE Ball Ball/Pad Number Function Bank Dual Function F11 PT21B 0 E10 PT21A 0 E9 PT20B 0 D9 PT20A 0 G10 PT19B 0 GND GNDIO0 - H10 PT19A 0 A5 PT18B 0 B5 PT18A 0 C7 PT17B 0 VCCIO VCCIO0 0 D7 ...

  • Page 190

    ... Lattice Semiconductor LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA LFE2-20E/20SE Ball Ball/Pad Number Function Bank Dual Function L12 VCC - L13 VCC - L14 VCC - L15 VCC - M11 VCC - M12 VCC - M15 VCC - M16 VCC - N11 VCC - N16 VCC - P11 VCC - P16 ...

  • Page 191

    ... Lattice Semiconductor LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA LFE2-20E/20SE Ball Ball/Pad Number Function Bank Dual Function U12 VCCIO5 5 V12 VCCIO5 5 Y9 VCCIO5 5 AA4 VCCIO6 6 R10 VCCIO6 6 R9 VCCIO6 6 T4 VCCIO6 6 V7 VCCIO6 6 F4 VCCIO7 7 J7 VCCIO7 7 L4 VCCIO7 7 M10 ...

  • Page 192

    ... Lattice Semiconductor LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA LFE2-20E/20SE Ball Ball/Pad Number Function Bank Dual Function C11 GND - C16 GND - C21 GND - C6 GND - F18 GND - F24 GND - F3 GND - F9 GND - J13 GND - J14 GND - J21 GND - J6 GND - K10 GND - K11 ...

  • Page 193

    ... Lattice Semiconductor LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA LFE2-20E/20SE Ball Ball/Pad Number Function Bank Dual Function U11 GND - U13 GND - U14 GND - U16 GND - U17 GND - V13 GND - V14 GND - V21 GND - V6 GND - P24 Supports true LVDS. Other differential signals must be emulated with external resistors. ...

  • Page 194

    ... Lattice Semiconductor LFE2-50E/SE and LFE2-70E/SE Logic Signal Connections: 672 fpBGA LFE2-50E/SE Ball Ball/Pad Number Function Bank Dual Function D2 PL2A 7 D1 PL2B 7 GND GNDIO7 - F6 PL5A 7 F5 PL5B 7 VCCIO VCCIO7 7 E4 PL6A 7 E3 PL6B 7 E2 PL7A 7 E1 PL7B 7 GND GNDIO7 - H6 PL8A 7 H5 PL8B ...

  • Page 195

    ... Lattice Semiconductor LFE2-50E/SE and LFE2-70E/SE Logic Signal Connections: 672 fpBGA LFE2-50E/SE Ball Ball/Pad Number Function Bank Dual Function L1 PL25A 7 LUM0_SPLLT_IN_A/LDQ24 VCCIO VCCIO7 7 M2 PL25B 7 LUM0_SPLLC_IN_A/LDQ24 M1 PL26A 7 LUM0_SPLLT_FB_A/LDQ24 N2 PL26B 7 LUM0_SPLLC_FB_A/LDQ24 GND GNDIO7 - M8 VCCPLL 7 VCCIO VCCIO7 7 GND GNDIO7 - N1 PL37A 7 L8 PL38A 7 K8 PL38B ...

  • Page 196

    ... Lattice Semiconductor LFE2-50E/SE and LFE2-70E/SE Logic Signal Connections: 672 fpBGA LFE2-50E/SE Ball Ball/Pad Number Function Bank Dual Function GND GNDIO6 - P3 PL54A 6 R3 PL54B 6 R4 PL55A 6 U2 PL55B 6 VCCIO VCCIO6 6 V2 PL56A 6 W2 PL56B 6 T6 PL57A 6 R5 PL57B 6 GND GNDIO6 - R6 PL58A 6 R7 ...

  • Page 197

    ... Lattice Semiconductor LFE2-50E/SE and LFE2-70E/SE Logic Signal Connections: 672 fpBGA LFE2-50E/SE Ball Ball/Pad Number Function Bank Dual Function VCCIO VCCIO6 6 Y6 PL73A 6 Y5 PL73B 6 AE2 PL74A 6 AD2 PL74B 6 GND GNDIO6 - AB3 PL75A 6 AB2 PL75B 6 W7 PL76A 6 VCCIO VCCIO6 6 W8 PL76B 6 Y7 ...

  • Page 198

    ... Lattice Semiconductor LFE2-50E/SE and LFE2-70E/SE Logic Signal Connections: 672 fpBGA LFE2-50E/SE Ball Ball/Pad Number Function Bank Dual Function AA10 PB21B 5 AC8 PB22A 5 AD8 PB22B 5 VCCIO VCCIO5 5 AB8 PB23A 5 AB10 PB23B 5 GND GNDIO5 - AE6 PB24A 5 AF6 PB24B 5 AA11 PB25A 5 AC9 PB25B 5 AB9 ...

  • Page 199

    ... Lattice Semiconductor LFE2-50E/SE and LFE2-70E/SE Logic Signal Connections: 672 fpBGA LFE2-50E/SE Ball Ball/Pad Number Function Bank Dual Function VCCIO VCCIO5 5 Y14 PB41A 5 AB14 PB41B 5 GND GNDIO5 - AE11 PB42A 5 AF11 PB42B 5 AD14 PB43A 5 AA15 PB43B 5 AE12 PB44A 5 PCLKT5_0/BDQ42 AF12 PB44B 5 PCLKC5_0/BDQ42 VCCIO ...

  • Page 200

    ... Lattice Semiconductor LFE2-50E/SE and LFE2-70E/SE Logic Signal Connections: 672 fpBGA LFE2-50E/SE Ball Ball/Pad Number Function Bank Dual Function W16 PB63A 4 AA17 PB63B 4 AF18 PB64A 4 AF19 PB64B 4 GND GNDIO4 - AA19 PB65A 4 W17 PB65B 4 Y19 PB66A 4 Y17 PB66B 4 AF20 PB67A 4 VCCIO VCCIO4 4 AE20 ...