LFE2M20E-6FN484C LATTICE SEMICONDUCTOR, LFE2M20E-6FN484C Datasheet - Page 238

• Manufacturer Part Number: LFE2M20E-6FN484C
• Description: FPGA LatticeECP2M Family 19000 Cells 90nm (CMOS) Technology 1.2V 484-Pin FBGA
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of LFE2M20E-6FN484C

• Package: 484FBGA
• Family Name: LatticeECP2M
• Device Logic Units: 19000
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 304
• Ram Bits: 1246208

Lattice Semiconductor
LFE2M-20E/SE and LFE2M-35E/SE Logic Signal Connections: 256 fpBGA
Number
GNDIO
VCCIO
GNDIO
VCCIO
GNDIO
VCCIO
GNDIO
VCCIO
GNDIO
VCCIO
GNDIO
VCCIO
GNDIO
VCCIO
Ball
M1
M4
M5
M6
N1
N2
N3
K6
N4
N6
K7
N5
P3
P4
P2
P1
R1
R2
R3
T2
R4
T3
T4
T5
T6
R6
P6
P7
T7
T8
L2
L3
L4
L5
L6
LLM0_PLLCAP
Function
Ball/Pad
GNDIO6
GNDIO6
GNDIO6
GNDIO5
GNDIO5
GNDIO5
GNDIO5
VCCIO6
VCCIO6
VCCIO5
VCCIO5
VCCIO5
VCCIO5
VCCIO4
PB10A
PB10B
PB16A
PB16B
PB17A
PB17B
PB22A
PB22B
PL42B
PL43A
PL43B
PL44A
PL44B
PL45A
PL45B
VCCJ
PB2A
PB2B
PB3A
PB3B
PB4A
PB4B
PB5A
PB5B
PB6A
PB6B
PB7A
PB7B
PB8A
PB8B
TMS
TDO
TCK
TDI
LFE2M20E/SE
Bank
6
6
6
6
6
6
5
5
5
5
5
5
5
5
5
5
5
5
5
6
6
6
6
5
5
5
5
5
5
5
5
5
5
5
4
4
4
-
-
-
-
-
-
-
-
-
-
-
-
LLM0_GPLLC_FB_A
LLM0_GDLLC_FB_A
LLM0_GDLLT_FB_A
LLM0_GPLLC_IN_A
LLM0_GPLLT_FB_A
LLM0_GDLLC_IN_A
LLM0_GDLLT_IN_A
PCLKC5_0/BDQ15
PCLKC4_0/BDQ24
PCLKT5_0/BDQ15
PCLKT4_0/BDQ24
VREF2_5/BDQ15
VREF1_5/BDQ15
Dual Function
BDQS6
BDQ6
BDQ6
BDQ6
BDQ6
BDQ6
BDQ6
BDQ6
BDQ6
BDQ6
BDQ6
BDQ6
BDQ6
BDQ6
BDQ6
BDQ6
Differential
C (LVDS)*
C (LVDS)*
T (LVDS)*
C
C
C
C
C
C
C
C
C
T
C
T
C
T
T
T
T
T
T
T
T
T
T
C
T
C
4-135
LLM0_PLLCAP
Function
Ball/Pad
GNDIO6
GNDIO6
GNDIO6
GNDIO5
GNDIO5
GNDIO5
GNDIO5
VCCIO6
VCCIO6
VCCIO5
VCCIO5
VCCIO5
VCCIO5
VCCIO4
PL57B
PL58A
PL58B
PL59A
PL59B
PL60A
PL60B
PB10A
PB10B
PB34A
PB34B
PB35A
PB35B
PB40A
PB40B
VCCJ
PB2A
PB2B
PB3A
PB3B
PB4A
PB4B
PB5A
PB5B
PB6A
PB6B
PB7A
PB7B
PB8A
PB8B
TCK
TMS
TDO
TDI
LatticeECP2/M Family Data Sheet
Bank
6
6
6
6
6
6
6
6
6
6
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
4
4
4
-
-
-
-
-
-
-
-
-
-
-
-
LFE2M35E/SE
LLM0_GDLLC_IN_A**/LDQ57
LLM0_GPLLC_IN_A**/LDQ57
LLM0_GDLLT_IN_A**/LDQ57
LLM0_GDLLC_FB_A/LDQ57
LLM0_GPLLC_FB_A/LDQ57
LLM0_GPLLT_FB_A/LDQ57
LLM0_GDLLT_FB_A/LDQ57
PCLKC5_0/BDQ33
PCLKC4_0/BDQ42
PCLKT5_0/BDQ33
PCLKT4_0/BDQ42
VREF2_5/BDQ33
VREF1_5/BDQ33
Function
BDQS6
BDQ6
BDQ6
BDQ6
BDQ6
BDQ6
BDQ6
BDQ6
BDQ6
BDQ6
BDQ6
BDQ6
BDQ6
BDQ6
BDQ6
BDQ6
Dual
Pinout Information
Differential
T (LVDS)*
C(LVDS)*
C(LVDS)*
C
C
C
C
C
C
C
C
C
C
C
C
C
T
T
T
T
T
T
T
T
T
T
T
T
T