LFE2M20E-6FN484C LATTICE SEMICONDUCTOR, LFE2M20E-6FN484C Datasheet - Page 38

• Manufacturer Part Number: LFE2M20E-6FN484C
• Description: FPGA LatticeECP2M Family 19000 Cells 90nm (CMOS) Technology 1.2V 484-Pin FBGA
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of LFE2M20E-6FN484C

• Package: 484FBGA
• Family Name: LatticeECP2M
• Device Logic Units: 19000
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 304
• Ram Bits: 1246208

Lattice Semiconductor
Figure 2-32. Output and Tristate Block, Top Edge
Tristate Register Block
The tristate register block provides the ability to register tri-state control signals from the core of the device before
they are passed to the sysI/O buffers. The block contains a register for SDR operation and an additional latch for
DDR operation. Figure 2-31 shows the diagram of the Tristate Register Block with the Output Block for the left, right
and bottom edges and Figure 2-32 shows the diagram of the Tristate Register Block with the Output Block for the
top edge.
In SDR mode, ONEG1 feeds one of the flip-flops that then feeds the output. The flip-flop can be configured a D-
type or latch. In DDR mode, ONEG1 and OPOS1 are fed into registers on the positive edge of the clock. Then in
the next clock the registered OPOS1 is latched. A multiplexer running off the same clock cycle selects the correct
register for feeding to the output (D0).
Control Logic Block
The control logic block allows the selection and modification of control signals for use in the PIO block. A clock is
selected from one of the clock signals provided from the general purpose routing, one of the edge clocks (ECLK1/
ECLK2) and a DQS signal provided from the programmable DQS pin and provided to the input register block. The
clock can optionally be inverted.
DDR Memory Support
Certain PICs have additional circuitry to allow the implementation of high speed source synchronous and DDR
memory interfaces. The support varies by the edge of the device as detailed below.
Left and Right Edges
PICs on these edges have registered elements that support DDR memory interfaces. One of every 16 PIOs con-
tains a delay element to facilitate the generation of DQS signals. The DQS signal feeds the DQS bus that spans the
set of 16 PIOs. Figure 2-33 shows the assignment of DQS pins in each set of 16 PIOs.
Bottom Edge
PICs on the bottom edge have registered elements that support DDR memory interfaces. One of every 18 PIOs
contains a delay element to facilitate the generation of DQS signals. The DQS signal feeds the DQS bus that spans
the set of 18 PIOs. Figure 2-34 shows the assignment of DQS pins in each set of 18 PIOs.
ONEG1
ONEG0
Note: Simplified version does not show CE and SET/RESET details.
(CLKA)
ECLK1
ECLK2
CLK1
TD
0
1
/LATCH
D
D
/LATCH
D-Type
2-35
D-Type
Q
Q
Tristate Logic
Output Logic
LatticeECP2/M Family Data Sheet
0
1
0
1
0
1
DO
TO
Architecture