LFE2M20E-6FN484C LATTICE SEMICONDUCTOR, LFE2M20E-6FN484C Datasheet - Page 54

• Manufacturer Part Number: LFE2M20E-6FN484C
• Description: FPGA LatticeECP2M Family 19000 Cells 90nm (CMOS) Technology 1.2V 484-Pin FBGA
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of LFE2M20E-6FN484C

• Package: 484FBGA
• Family Name: LatticeECP2M
• Device Logic Units: 19000
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 304
• Ram Bits: 1246208

Hot Socketing Specifications
Lattice Semiconductor
I
I
1. V
2. 0
3. I
4. LVCMOS and LVTTL only.
5. Assumes that the device is powered down with all supplies grounded, both P and N inputs driven by a CML driver with maximum allowed
V
1. If V
2. See recommended voltages by I/O standard in subsequent table.
3. V
4. For proper power-up configuration, users must ensure that the configuration control signals such as the CFGx, INITN, PROGRAMN and
5. For power-up, V
6. V
7. For more power supply design recommendations, refer to TN1114
DK
HDIN
CCP
Symbol
ECP2-12 and ECP2-20 only).
V
nected to the same power supply as V
decoupling.
DONE pins are driven to the proper logic levels when the device powers up. The device power-up is triggered by the last of V
V
(configuration I/O bank) voltage must be powered up prior to or at the same time as the last of VCC or VCCAUX reaches its minimum lev-
els.
DK
CC
CCIB
CCAUX
CCIO8
CCRX

5
6
CCIO
is additive to I
V
, V
CC
Symbol
of 1.575V, 8b10b data and internal AC coupling.
,V
CCAUX
supplies that reaches its minimum valid levels. Alternatively, if the configuration control signals are pulled up by V
ramp rate must not exceed 30mV/µs during power-up when transitioning between 0V and 3.3V.
or V

CCTX
V
CC
CCJ
Input or I/O leakage current
SERDES average input current when
device is powered down and inputs
are driven
and V
and V
(MAX), 0
CC
is set to 1.2V, they must be connected to the same power supply as V
PU
must reach its valid minimum value before powering up V
CCIO
, I
CCP
PW
should rise/fall monotonically. V
must be tied together in each quad and all quads need to be powered up.

PLL and Reference Clock Buffer Power
or I
V
Parameter
CCIO
BH
.

V
CCIO
CCAUX
(MAX) or 0
. V
CCPLL
1, 2, 3, 4
must be connected to the same power supply as V

V
CC
0  V
Parameter
CCAUX
and V
IN

 V
CCPLL
3-2
V
Electrical Recommendations for Lattice
Condition
CCAUX
IH
(MAX.)
must be connected to the same power supply (applies to ECP2-6,
(MAX).
CCAUX
(LatticeECP2/M “S” version devices only).
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
CC.
If V
CCIO
Min.
—
—
or V
CCJ
CC
Min.
1.14
Typ.
SERDES.
is set to 3.3V, they must be con-
—
—
through careful filtering and
+/-1000
Max.
Max.
1.26
CCIO8
4
CC
, the V
, V
CCAUX
Units
Units
mA
µA
V
CCIO8
or