LFE2M20E-6FN484C LATTICE SEMICONDUCTOR, LFE2M20E-6FN484C Datasheet - Page 9

• Manufacturer Part Number: LFE2M20E-6FN484C
• Description: FPGA LatticeECP2M Family 19000 Cells 90nm (CMOS) Technology 1.2V 484-Pin FBGA
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of LFE2M20E-6FN484C

• Package: 484FBGA
• Family Name: LatticeECP2M
• Device Logic Units: 19000
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 304
• Ram Bits: 1246208

Architecture
Lattice Semiconductor
LatticeECP2/M Family Data Sheet
ROM Mode
ROM mode uses the LUT logic; hence, Slices 0 through 3 can be used in ROM mode. Preloading is accomplished
through the programming interface during PFU configuration.
Routing
There are many resources provided in the LatticeECP2/M devices to route signals individually or as busses with
related control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing)
segments.
The inter-PFU connections are made with x1 (spans two PFU), x2 (spans three PFU) and x6 (spans seven PFU).
The x1 and x2 connections provide fast and efficient connections in horizontal and vertical directions. The x2 and
x6 resources are buffered, allowing the routing of both short and long connections between PFUs.
The LatticeECP2/M family has an enhanced routing architecture that produces a compact design. The Diamond
and ispLEVER design software takes the output of the synthesis tool and places and routes the design. Generally,
the place and route tool is completely automatic, although an interactive routing editor is available to optimize the
design.
sysCLOCK Phase Locked Loops (GPLL/SPLL)
The sysCLOCK PLLs provide the ability to synthesize clock frequencies. All the devices in the LatticeECP2/M fam-
ily support two General Purpose PLLs (GPLLs) which are full-featured PLLs. In addition, some of the larger devices
have two to six Standard PLLs (SPLLs) that have a subset of GPLL functionality.
General Purpose PLL (GPLL)
The architecture of the GPLL is shown in Figure 2-5. A description of the GPLL functionality follows.
CLKI is the reference frequency (generated either from the pin or from routing) for the PLL. CLKI feeds into the
Input Clock Divider block. The CLKFB is the feedback signal (generated from CLKOP or from a user clock PIN/
logic). This signal feeds into the Feedback Divider. The Feedback Divider is used to multiply the reference fre-
quency.
The Delay Adjust Block adjusts either the delays of the reference or feedback signals. The Delay Adjust Block can
either be programmed during configuration or can be adjusted dynamically. The setup, hold or clock-to-out times of
the device can be improved by programming a delay in the feedback or input path of the PLL, which will advance or
delay the output clock with reference to the input clock.
Following the Delay Adjust Block, both the input path and feedback signals enter the Voltage Controlled Oscillator
(VCO) block. In this block the difference between the input path and feedback signals is used to control the fre-
quency and phase of the oscillator. A LOCK signal is generated by the VCO to indicate that the VCO has locked
onto the input clock signal. In dynamic mode, the PLL may lose lock after a dynamic delay adjustment and not
relock until the t
parameter has been satisfied. LatticeECP2/M devices have two dedicated pins on the left and
LOCK
right edges of the device for connecting optional external capacitors to the VCO. This allows the PLLs to operate at
a lower frequency. This is a shared resource that can only be used by one PLL (GPLL or SPLL) per side.
The output of the VCO then enters the post-scalar divider. The post-scalar divider allows the VCO to operate at
higher frequencies than the clock output (CLKOP), thereby increasing the frequency range. A secondary divider
takes the CLKOP signal and uses it to derive lower frequency outputs (CLKOK). The Phase/Duty Select block
adjusts the phase and duty cycle of the CLKOP signal and generates the CLKOS signal. The phase/duty cycle set-
ting can be pre-programmed or dynamically adjusted.
The primary output from the post scalar divider CLKOP along with the outputs from the secondary divider (CLKOK)
and Phase/Duty select (CLKOS) are fed to the clock distribution network.
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