IDT5T9306NLI IDT, Integrated Device Technology Inc, IDT5T9306NLI Datasheet

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IDT5T9306NLI

Manufacturer Part Number
IDT5T9306NLI
Description
Manufacturer
IDT, Integrated Device Technology Inc
Type
Clock Driverr
Datasheet

Specifications of IDT5T9306NLI

Number Of Clock Inputs
2
Mode Of Operation
Differential
Output Frequency
1000MHz
Output Logic Level
LVDS
Operating Supply Voltage (min)
2.3V
Operating Supply Voltage (typ)
2.5V
Operating Supply Voltage (max)
2.7V
Package Type
VFQFPN
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
28
Quiescent Current
240mA
Lead Free Status / RoHS Status
Not Compliant
2.5V LVDS 1:6 CLOCK BUFFER
TERABUFFER™ II
FEATURES:
• Guaranteed Low Skew < 25ps (max)
• Very low duty cycle distortion < 125ps (max)
• High speed propagation delay < 1.75ns (max)
• Additive phase jitter, RMS 0.159ps (typical) @ 125MHz
• Up to 1GHz operation
• Selectable inputs
• Hot insertable and over-voltage tolerant inputs
• 3.3V / 2.5V LVTTL, HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V),
• Selectable differential inputs to six LVDS outputs
• Power-down mode
• 2.5V V
• Available in VFQFPN package
APPLICATIONS:
• Clock distribution
FUNCTIONAL BLOCK DIAGRAM
IDT
CML, or LVDS input interface
/ ICS
DD
LVDS CLOCK BUFFER TERABUFFER™ II
SEL
PD
GL
A1
A1
A2
A2
G
0
1
1
DESCRIPTION:
input to six LVDS outputs. The fanout from a differential input to six LVDS outputs
reduces loading on the preceding driver and provides an efficient clock
distribution network. The IDT5T9306 can act as a translator from a differential
HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML, or LVDS input to
LVDS outputs. A single-ended 3.3V / 2.5V LVTTL input can also be used to
translate to LVDS outputs. The redundant input capability allows for an
asynchronous change-over from a primary clock source to a secondary clock
source. Selectable reference inputs are controlled by SEL.
disabled, the outputs will drive to the value selected by the GL pin. Multiple power
and grounds reduce noise.
The IDT5T9306 2.5V differential clock buffer is a user-selectable differential
The IDT5T9306 outputs can be asynchronously enabled/disabled. When
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
IDT5T9306 REV. B October 21, 2008
IDT5T9306
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Q5
Q5
Q6
Q6

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IDT5T9306NLI Summary of contents

Page 1

LVDS 1:6 CLOCK BUFFER TERABUFFER™ II FEATURES: • Guaranteed Low Skew < 25ps (max) • Very low duty cycle distortion < 125ps (max) • High speed propagation delay < 1.75ns (max) • Additive phase jitter, RMS 0.159ps (typical) @ ...

Page 2

IDT5T9306 2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II PIN CONFIGURATION IDT ™ / ICS ™ LVDS CLOCK BUFFER TERABUFFER™ II ...

Page 3

IDT5T9306 2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II ABSOLUTE MAXIMUM RATINGS Symbol Description V Power Supply Voltage DD V Input Voltage I (2) V Output Voltage O T Storage Temperature STG T Junction Temperature J NOTES: 1. Stresses greater than ...

Page 4

IDT5T9306 2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR LVTTL Symbol Parameter Input Characteristics I Input HIGH Current IH I Input LOW Current IL V Clamp Diode Voltage Input Voltage IN ...

Page 5

IDT5T9306 2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II DIFFERENTIAL INPUT AC TEST CONDITIONS FOR HSTL Symbol Parameter V Input Signal Swing (1) DIF V Differential Input Signal Crossing Point X D Duty Cycle H V Input Timing Measurement Reference Level ...

Page 6

IDT5T9306 2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II DIFFERENTIAL INPUT AC TEST CONDITIONS FOR LVDS Symbol Parameter V Input Signal Swing (1) DIF V Differential Input Signal Crossing Point X D Duty Cycle H V Input Timing Measurement Reference Level ...

Page 7

IDT5T9306 2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Symbol Parameter Skew Parameters Same Device Output Pin-to-Pin Skew Pulse Skew Part-to-Part ...

Page 8

IDT5T9306 2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II DIFFERENTIAL AC TIMING WAVEFORMS 1/ [1:2] [1:2] t PLH SK( NOTES: 1. Pulse skew is calculated using the following expression ...

Page 9

IDT5T9306 2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ [1:2] [1: PLH Differential Gate Disable/Enable Showing Runt Pulse Generation NOTE shown possible to generate runt pulses on gate ...

Page 10

IDT5T9306 2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II TEST CIRCUITS AND CONDITIONS Pulse Generator DIFFERENTIAL INPUT TEST CONDITIONS IDT ™ / ICS ™ LVDS CLOCK BUFFER TERABUFFER™ II ~50Ω Transmission Line ~50Ω Transmission Line Test Circuit ...

Page 11

IDT5T9306 2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II Pulse Generator A Pulse Generator A Test Circuit for Propagation, Skew, and Gate Enable/Disable Timing NOTES: 1. Specifications only apply to "Normal Operations" test condition. The T 2. The scope inputs are ...

Page 12

IDT5T9306 2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II RECOMMENDED LANDING PATTERN NOTE: All dimensions are in millimeters. IDT ™ / ICS ™ LVDS CLOCK BUFFER TERABUFFER™ pin 12 IDT5T9306 REV. B October 21, 2008 ...

Page 13

IDT5T9306 2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II July 23, 2002 Datasheet creation October 8, 2002 Page 1, entire page changed; page 2, both diagrams; page 3, Pin Description and notes; page 4, DC Cha. for LVPECL and Differential Input ...

Page 14

IDT5T9306 2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II ORDERING INFORMATION XX XXXXX Package Device Type Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT © 2008 Integrated Device ...

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