ICS8305AGI IDT, Integrated Device Technology Inc, ICS8305AGI Datasheet

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ICS8305AGI

Manufacturer Part Number
ICS8305AGI
Description
Manufacturer
IDT, Integrated Device Technology Inc
Type
Clock Driverr
Datasheet

Specifications of ICS8305AGI

Number Of Clock Inputs
2
Output Frequency
350MHz
Output Logic Level
LVCMOS/LVTTL
Operating Supply Voltage (min)
3.135V
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.465V
Package Type
TSSOP
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
16
Lead Free Status / RoHS Status
Not Compliant

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G
The ICS8305I is a low skew, 1-to-4, Differential/LVCMOS-to-
LVCMOS/LVTTL Fanout Buffer. The ICS8305I has selectable
clock inputs that accept either differential or single ended
input levels. The clock enable is internally synchronized to
eliminate runt pulses on the outputs during asynchronous
assertion/deassertion of the clock enable pin. Outputs are
forced LOW when the clock is disabled. A separate output
enable pin controls whether the outputs are in the active or
high impedance state.
Guaranteed output and part-to-part skew characteristics make
the ICS8305I ideal for those applications demanding well de-
fined performance and repeatability.
B
8305AGI
LVCMOS_CLK
LOCK
ENERAL
CLK_SEL
CLK_EN
nCLK
CLK
D
OE
IAGRAM
D
ESCRIPTION
0
1
0
1
D
LE
Q
Q0
Q1
Q2
Q3
LVCMOS-
www.idt.com
L
OW
1
F
• 4 LVCMOS/LVTTL outputs
• Selectable differential or LVCMOS/LVTTL clock inputs
• CLK, nCLK pair can accept the following differential
• LVCMOS_CLK supports the following input types:
• Maximum output frequency: 350MHz
• Output skew: 40ps (maximum)
• Part-to-part skew: 700ps (maximum)
• 3.3V core, 3.3V, 2.5V or 1.8V output operating supply
• -40°C to 85°C ambient operating temperature
• Lead-Free package fully RoHS compliant
P
S
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
LVCMOS, LVTTL
Additive phase jitter, RMS: 0.04ps (typical)
EATURES
IN
KEW
A
TO
4.4mm x 3.0mm x 0.92mm package body
, 1-
SSIGNMENT
-LVCMOS/LVTTL F
LVCMOS_CLK
TO
CLK_SEL
CLK_EN
-4, M
nCLK
GND
CLK
V
OE
16-Lead TSSOP
DD
ICS8305I
G Package
Top View
ULTIPLEXED
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Q0
V
Q1
GND
Q2
V
Q3
GND
DDO
DDO
ANOUT
ICS8305I
D
IFFERENTIAL
REV. B JULY 29, 2010
B
UFFER
/

Related parts for ICS8305AGI

ICS8305AGI Summary of contents

Page 1

G D ENERAL ESCRIPTION The ICS8305I is a low skew, 1-to-4, Differential/LVCMOS-to- LVCMOS/LVTTL Fanout Buffer. The ICS8305I has selectable clock inputs that accept either differential or single ended input levels. The clock enable is internally synchronized to eliminate runt pulses ...

Page 2

ABLE IN ESCRIPTIONS ...

Page 3

T 3A ABLE ONTROL NPUT UNCTION ...

Page 4

BSOLUTE AXIMUM ATINGS Supply Voltage Inputs Outputs Package Thermal Impedance, JA Storage Temperature, T STG T 4A ABLE OWER UPPLY HARACTERISTICS ...

Page 5

T 4C ABLE IFFERENTIAL HARACTERISTICS ...

Page 6

T 5B 3.3V ± 5%, V ABLE HARACTERISTICS ...

Page 7

The spectral purity in a band at a specific offset from the funda- mental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most ...

Page 8

P ARAMETER 1.65V± DDO LVCMOS GND -1.65V±5% 3.3V C /3. ORE UTPUT OAD 2.4V±0.09V 0.9V±0.075V DDO LVCMOS GND -0.9V±0.075V 3.3V C /1. ORE UTPUT OAD ...

Page 9

LVCMOS_CLK nCLK CLK V DDO 2 Q0:Q3 ➤ ➤ ROPAGATION ELAY V DDO 2 Q0: PERIOD 100% odc = t PERIOD ...

Page 10

IRING THE IFFERENTIAL NPUT TO Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = V generated by the bias resistors R1, R2 and C1. This bias ...

Page 11

IFFERENTIAL LOCK NPUT NTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both V SWING the V and V input requirements. Figures show PP CMR interface examples for ...

Page 12

S E CHEMATIC XAMPLE This application note provides general design guide using ICS8305I LVCMOS buffer. Figure 4 shows a schematic example of the ICS8305I LVCMOS clock buffer. In this example, the input VDD VDD Zo = ...

Page 13

ACKAGE UTLINE UFFIX FOR 8305AGI KEW TO LVCMOS- -LVCMOS/LVTTL F TO TSSOP EAD ABLE ACKAGE IMENSIONS ...

Page 14

ABLE RDERING NFORMATION ...

Page 15

& ...

Page 16

We’ve Got Your Timing Solution. 6024 Silver Creek Valley Road San Jose, CA 95138 © 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of ...

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