ICS8305AGT IDT, Integrated Device Technology Inc, ICS8305AGT Datasheet

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ICS8305AGT

Manufacturer Part Number
ICS8305AGT
Description
Manufacturer
IDT, Integrated Device Technology Inc
Type
Clock Driverr
Datasheet

Specifications of ICS8305AGT

Number Of Clock Inputs
2
Output Frequency
350MHz
Output Logic Level
LVCMOS/LVTTL
Operating Supply Voltage (min)
3.135V
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.465V
Package Type
TSSOP
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
16
Lead Free Status / RoHS Status
Not Compliant
Block Diagram
LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/
LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
General Description
either differential or single ended input levels. The clock enable is
internally synchronized to eliminate runt pulses on the outputs
during asynchronous assertion/deassertion of the clock enable
pin. Outputs are forced LOW when the clock is disabled. A
separate output enable pin controls whether the outputs are in the
active or high impedance state.
Guaranteed output and part-to-part skew characteristics make the
ICS8305 ideal for those applications demanding well defined
performance and repeatability.
LVCMOS_CLK
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
HiPerClockS™
ICS
CLK_SEL
CLK_EN
nCLK
CLK
OE
Pullup
Pulldown
Pulldown
Pullup/
Pulldown
Pullup
Pullup
The ICS8305 is a low skew, 1-to-4, Differential/
LVCMOS-to-LVCMOS/LVTTL Fanout Buffer and a
member of the HiPerClockS™ family of High
Performance Clock Solutions from IDT. The
ICS8305 has selectable clock inputs that accept
0
1
0
1
D
LE
Q
Q3
Q0
Q1
Q2
1
Features
Four LVCMOS / LVTTL outputs, 7
Selectable differential or LVCMOS / LVTTL clock inputs
CLK, nCLK pair can accept the following differential input levels:
LVPECL, LVDS, LVHSTL, HCSL, SSTL
LVCMOS_CLK supports the following input types: LVCMOS,
LVTTL
Maximum output frequency: 350MHz
Output skew: 35ps (maximum)
Part-to-part skew: 700ps (maximum)
Power supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
3.3V/1.5V
0°C to 70°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Additive phase jitter, RMS: 0.04ps (typical)
Pin Assignment
LVCMOS_CLK
4.4mm x 3.0mm x 0.925mm
CLK_SEL
CLK_EN
ICS8305AG REV. C OCTOBER 23, 2008
nCLK
GND
CLK
V
16-Lead TSSOP
OE
DD
package body
G Package
ICS8305
1
2
3
4
5
6
7
8
output impedance
16
15
14
13
12
11
10
9
Q0
Q1
GND
Q2
Q3
V
V
DDO
DDO
ICS8305

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ICS8305AGT Summary of contents

Page 1

LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/ LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER General Description The ICS8305 is a low skew, 1-to-4, Differential/ ICS LVCMOS-to-LVCMOS/LVTTL Fanout Buffer and a member of the HiPerClockS™ family of High HiPerClockS™ Performance Clock Solutions from IDT. The ICS8305 has ...

Page 2

ICS8305 LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER Table 1. Pin Descriptions Number Name GND CLK_EN 5 CLK 6 nCLK 7 CLK_SEL 8 LVCMOS_CLK 10, 12, 14, 16 Q3, Q2, Q1, ...

Page 3

ICS8305 LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER Function Tables Table 3. Control Input Function Table OE CLK_EN After CLK_EN switches, the clock outputs are disabled or enabled following a ...

Page 4

ICS8305 LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions ...

Page 5

ICS8305 LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER Table 4B. LVCMOS/LVTTL DC Characteristics, T Symbol Parameter CLK_EN, CLK_SEL, OE Input High V IH Voltage LVCMOS_CLK CLK_EN, CLK_SEL, OE Input Low V IL Voltage LVCMOS_CLK CLK_EN, CLK_SEL, OE Input I IH ...

Page 6

ICS8305 LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER AC Electrical Characteristics Table 5A. AC Characteristics, V Parameter Symbol f Output Frequency MAX LVCMOS_CLK; Propagation NOTE 1A tp Delay, LH CLK/nCLK; Low to High NOTE 1B tsk(o) Output Skew; NOTE 2, ...

Page 7

ICS8305 LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER Table 5C. AC Characteristics, V Parameter Symbol f Output Frequency MAX LVCMOS_CLK; Propagation NOTE 1A tp Delay, LH CLK/nCLK; Low to High NOTE 1B tsk(o) Output Skew; NOTE 2, 6 tsk(pp) Part-to-Part ...

Page 8

ICS8305 LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER Additive Phase Jitter The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is ...

Page 9

ICS8305 LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER Parameter Measurement Information 1.65V±5% V DD, V DDO LVCMOS C 25pF* L *For t /t measurement only -1.65V± 3.3V Core/3.3V LVCMOS Output Load AC Test Circuit 2.4V±0.09V 0.9V±0.075V V DD ...

Page 10

ICS8305 LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER Parameter Measurement Information, continued Part 1 V DDO Qx 2 Part 2 V DDO Qy 2 tsk(pp) Part-to-Part Skew 80% 20% Clock t Outputs R Output Rise/Fall Time IDT™ / ICS™ LVCMOS/LVTTL ...

Page 11

ICS8305 LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER Application Information Recommendations for Unused Input and Output Pins Inputs: LVCMOS_CLK Input For applications not requiring the use of a clock input, it can be left floating. Though not required, but for ...

Page 12

ICS8305 LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER Differential Clock Input Interface The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both signals must meet the V V input requirements. Figures show interface ...

Page 13

ICS8305 LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER Schematic Example This application note provides general design guide using ICS8305 LVCMOS buffer. Figure 4 shows a schematic example of the ICS8305 LVCMOS clock buffer. In this example, the input is VDD ...

Page 14

ICS8305 LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER Reliability Information θ Table 6. vs. Air Flow Table for a 16 Lead TSSOP JA Linear Feet per Minute Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards NOTE: ...

Page 15

ICS8305 LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER Ordering Information Table 8. Ordering Information Part/Order Number Marking 8305AG 8305AG 8305AGT 8305AG 8305AGLF 8305AGLF 8305AGLFT 8305AGLF NOTE: Parts that are ordered with an "LF" suffix to the part number are the ...

Page 16

... C IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER Description of Change Ordering Information table - corrected Part/Order Number typo from ICS88305AGT to ICS8305AGT. Added Additive Phase Jitter to AC Characteristics Tables. Added Additive Phase Jitter Section. Pin Description Table - corrected CLK_EN description. Features Section - added 1.5V output to Supply Mode bullet and added Lead-Free buttlet ...

Page 17

ICS8305 LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United ...

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