ICS8305AG IDT, Integrated Device Technology Inc, ICS8305AG Datasheet
ICS8305AG
Specifications of ICS8305AG
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ICS8305AG Summary of contents
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... Available in both standard (RoHS 5) and lead-free (RoHS 6) packages ICS8305 Ω output impedance Pin Assignment Q0 GND DDO CLK_EN 4 GND 12 CLK nCLK V DDO 10 7 CLK_SEL LVCMOS_CLK ICS8305 16-Lead TSSOP 4.4mm x 3.0mm x 0.925mm package body G Package ICS8305AG REV. C OCTOBER 23, 2008 ...
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... LVCMOS_CLK input. LVCMOS/LVTTL interface levels. Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. Single-ended clock outputs. 7 Output LVCMOS/LVTTL interface levels. Power Output supply pins. Test Conditions 2 Ω output impedance. Minimum Typical Maximum ICS8305AG REV. C OCTOBER 23, 2008 Units pF Ω k Ω Ω ...
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... After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1. Disabled nCLK CLK, LVCMOS_CLK CLK_EN Q0:Q3 Figure 1. CLK_EN Timing Diagram IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER Inputs CLK_SEL Selected Source 0 LVCMOS_CLK 1 CLK/nCLK 0 LVCMOS_CLK 1 CLK/nCLK X 3 Outputs Q0:Q3 Disabled; Low Disabled; Low Enabled Enabled Hi-Z Enabled ICS8305AG REV. C OCTOBER 23, 2008 ...
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... V = 3.3V±5% or 2.5V±5% or 1.8V±0.5V or 1.5V±5%, DD DDO Test Conditions Minimum 3.135 3.135 2.375 1.65 1.425 4 Typical Maximum Units 3.3 3.465 V 3.3 3.465 V 2.5 2.625 V 1.8 1.95 V 1.5 1.575 ICS8305AG REV. C OCTOBER 23, 2008 ...
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... CLK V = 3.465V Minimum Typical 2 2 -0.3 -0 -150 2.6 1.8 1 0.3 DDO -5 Minimum Typical -150 -5 0.15 GND + 0.5 ICS8305AG REV. C OCTOBER 23, 2008 Maximum Units 0 µA 150 µA µA µ 0.5 V 0.5 V 0.4 V 0.35 V µA 5 µA Maximum Units 150 µ ...
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... Test Conditions Measured on the Rising Edge 20% to 80% Ref = CLK/nCLK Ref = LVCMOS_CLK, ƒ ≤ 300MHz 6 Minimum Typical 1.75 0.04 100 45 45 /2. = 0°C to 70°C A Minimum Typical 1.8 0.04 100 44 44 ICS8305AG REV. C OCTOBER 23, 2008 Maximum Units 350 MHz 2. 700 ps ps 700 /2. ...
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... Measured on the Rising Edge 20% to 80% ƒ ≤ 166MHz ƒ > 166MHz 7 = 0°C to 70°C A Minimum Typical 1.95 0.04 100 44 44 /2. = 0°C to 70°C A Minimum Typical 2 0.04 200 45 42 ICS8305AG REV. C OCTOBER 23, 2008 Maximum Units 350 MHz 3. 900 ps ps 700 /2. DDO ...
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... Offset Frequency (Hz) device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. 8 Additive Phase Jitter at 155.52MHz = 0.04ps (typical) 1M 10M 100M ICS8305AG REV. C OCTOBER 23, 2008 ...
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... Core/2.5V LVCMOS Output Load AC Test Circuit 2.55V±5% SCOPE LVCMOS -0.9V±0.75V 3.3V Core/1.5V LVCMOS Output Load AC Test Circuit Qx V CMR Qy Output Skew 9 1.25V±5% V DDO Qx GND -1.25V±5% 0.75V±5% V DDO Qx GND V CCO 2 V CCO 2 tsk(b) ICS8305AG REV. C OCTOBER 23, 2008 SCOPE SCOPE ...
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... Part-to-Part Skew 80% 20% Clock t Outputs R Output Rise/Fall Time IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER Q0:Q3 Output Duty Cycle/Pulse Width/Period LVCMOS_CLK 80% nCLK CLK 20 Q0:Q3 Propagation Delay 10 V DDO PERIOD 100% odc = t PERIOD V DDO 2 V DDO 2 ➤ ➤ ICS8305AG REV. C OCTOBER 23, 2008 ...
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... All unused LVCMOS output can be left floating. There should be no trace attached. R1 and R2 might need to be adjusted to position the V_REF in the /2 is center of the input voltage swing. For example, if the input clock DD swing is only 2.5V and V R2/R1 = 0.609 CLK nCLK 3.3V, V_REF should be 1.25V and DD ICS8305AG REV. C OCTOBER 23, 2008 ...
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... R2 50 Driven by a 3.3V LVPECL Driver 100 LVDS Driven by a 3.3V LVDS Driver 2. 120 120 SSTL R1 R2 120 120 Driven by a 2.5V SSTL Driver ICS8305AG REV. C OCTOBER 23, 2008 3.3V CLK nCLK HiPerClockS Input 3.3V CLK nCLK Receiver 3.3V CLK nCLK HiPerClockS ...
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... LVCMOS driver. CLK_EN is set at logic low to select LVCMOS_CLK input. VDD GND VDDO 3 14 VDD CLK_EN GND 5 12 CLK nCLK VDDO 7 10 CLK_SEL LVCMOS_CLK GND R6 ICS8305 1K (U1,3) VDD C1 VDD=3.3V 0. LVCMOS Receiv (U1,11) (U1,15) LVCMOS Receiv 0.1u 0.1u ICS8305AG REV. C OCTOBER 23, 2008 ...
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... All Dimensions in Millimeters Symbol Minimum 0.5 A2 0.80 b 0.19 c 0. 0.45 α 0° aaa Reference Document: JEDEC Publication 95, MO-153 ICS8305AG REV. C OCTOBER 23, 2008 14 500 106.8°C/W 78.1°C/W Maximum 16 1.20 0.15 1.05 0.30 0.20 5.10 6.40 Basic 4.50 0.65 Basic 0.75 8° 0.10 ...
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... Shipping Packaging 16 Lead TSSOP 16 Lead TSSOP 2500 Tape & Reel “Lead-Free” 16 Lead TSSOP “Lead-Free” 16 Lead TSSOP 2500 Tape & Reel 15 Temperature Tube 0°C to 70°C 0°C to 70°C Tube 0°C to 70°C 0°C to 70°C ICS8305AG REV. C OCTOBER 23, 2008 ...
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... LVCMOS DC Characteristics Table - added V Added 3.3V/1.5V AC Characteristics Table. Added 3.3V/1.5V Output Load AC Test Circuit Drawing. Added Recommendations for Unused Input and Output Pins. Added Lead-Free part number. Ordering Information Table - added lead-free marking. Corrected non-lead free marking from ICS8305AG to 8305AG. 16 1/20/04 2/26/04 12/6/04 1.5V. ...
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ICS8305 LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United ...