KSZ8864RMN Micrel Inc, KSZ8864RMN Datasheet
KSZ8864RMN
Specifications of KSZ8864RMN
KSZ8864RMN
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KSZ8864RMN Summary of contents
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... The KSZ8864RMN contains four MACs and two PHYs. The two PHYs support the 10/100Base-T/TX. All registers of MACs and PHYs units can be managed by the control interface of SPI or the SMI ...
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Features Advanced Switch Features • IEEE 802.1q VLAN support for up to 128 VLAN groups (full-range 4096 of VLAN IDs). • Static MAC table supports entries. • VLAN ID tag/untag options, per port basis. • IEEE 802.1p/q ...
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... Set-top/Game Box • Automotive • Industrial Control • IPTV POF Ordering Information Part Number Junction Temperature Range KSZ8864RMN 0°C to 70°C (1) −40°C to +85°C KSZ8864RMNI Note: 1. Please consult sales for the availability Revision History Revision 1.0 10/29/10 1.1 12/16/10 1.2 01/20/11 January 2011 • ...
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Contents Pin Configuration ..........................................................................................................................................................13 Pin Description ..............................................................................................................................................................14 Pin for Strap-in Options................................................................................................................................................19 Introduction ...................................................................................................................................................................22 Functional Overview: Physical Layer Transceiver ....................................................................................................22 100BASE-TX Transmit ...............................................................................................................................................22 100BASE-TX Receive ................................................................................................................................................22 PLL Clock Synthesizer................................................................................................................................................22 Scrambler/De-Scrambler (100BASE-TX only)............................................................................................................23 10BASE-T Transmit....................................................................................................................................................23 10BASE-T Receive .....................................................................................................................................................23 MDI/MDI-X Auto Crossover ........................................................................................................................................23 ...
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Port-Based Priority..................................................................................................................................................36 802.1p-Based Priority .............................................................................................................................................36 DiffServ-Based Priority ...........................................................................................................................................37 Spanning Tree Support...............................................................................................................................................37 Rapid Spanning Tree Support ....................................................................................................................................38 Tail Tagging Mode ......................................................................................................................................................39 IGMP Support .............................................................................................................................................................40 Port Mirroring Support ................................................................................................................................................40 VLAN Support .............................................................................................................................................................40 Rate Limiting Support .................................................................................................................................................41 Ingress Rate Limit...................................................................................................................................................41 Egress Rate Limit ...
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Register 17 (0x11): Reserved.................................................................................................................................61 Register 33 (0x21): Port 1 Control 1.......................................................................................................................61 Register 49 (0x31): Port 2 Control 1.......................................................................................................................61 Register 65 (0x41): Port 3 Control 1.......................................................................................................................61 Register 81 (0x51): Port 4 Control 1.......................................................................................................................61 Register 18 (0x12): Reserved.................................................................................................................................61 Register 34 (0x22): Port ...
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Register 61 (0x3D): Port 2 Control 13 ....................................................................................................................66 Register 77 (0x4D): Reserved ................................................................................................................................66 Register 93 (0x5D): Reserved ................................................................................................................................66 Register 30 (0x1E): Reserved ................................................................................................................................67 Register 46 (0x2E): Port 1 Status 1........................................................................................................................67 Register 62 (0x3E): Port 2 Status 1........................................................................................................................67 Register 78 (0x4E): ...
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Register 146 (0x92): TOS Priority Control Register 2 ............................................................................................74 Register 147 (0x93): TOS Priority Control Register 3 ............................................................................................74 Register 148 (0x94): TOS Priority Control Register 4 ............................................................................................74 Register 149 (0x95): TOS Priority Control Register 5 ............................................................................................74 Register 150 (0x96): TOS ...
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Register 245 (0xF5): Port 4 Control 13...................................................................................................................78 Register 182 (0xB6): Reserved ..............................................................................................................................79 Register 198 (0xC6): Port 1 Rate Limit Control ......................................................................................................79 Register 214 (0xD6): Port 2 Rate Limit Control ......................................................................................................79 Register 230 (0xE6): Port 3 Rate Limit Control ......................................................................................................79 Register ...
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Register 222 (0xDE): Port 2 Queue 3 Egress Limit Control 4 ................................................................................82 Register 238 (0xEE): Port 3 Queue 3 Egress Limit Control 4 ................................................................................82 Register 254 (0xFE): Port 4 Queue 3 Egress Limit Control 4 ................................................................................82 Data Rate Selection Table ...
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... Figure 4. Destination Address Lookup Flow Chart, Stage 1 ........................................................................................ 30 Figure 5. Destination Address Resolution Flow Chart – Stage 2................................................................................. 31 Figure 6. 802.1p Priority Field Format.......................................................................................................................... 37 Figure 7. Tail Tag Frame Format .................................................................................................................................. 39 Figure 8. KSZ8864RMN EEPROM Configuration Timing Diagram ............................................................................. 43 Figure 9. SPI Write Data Cycle .................................................................................................................................... 44 Figure 10. SPI Read Data Cycle .................................................................................................................................. 44 Figure 11. SPI Multiple Write ....................................................................................................................................... 45 Figure 12 ...
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List of Tables Table 1. MDI/MDI-X Pin Definitions ............................................................................................................................. 23 Table 2. Internal Function Block Status ........................................................................................................................ 27 Table 3. Switch MAC 3 SW3-MII and MAC 4 SW4- MII Signals.................................................................................. 33 Table 4. MAC3 SW3-RMII and MAC4 SW4-RMII Connection..................................................................................... 35 ...
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Pin Configuration January 2011 64-Pin QFN 13 M9999-012011-1.2 ...
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Pin Description Pin Number Pin Name 1 RXP1 2 RXM1 3 TXP1 4 TXM1 5 VDDA12 6 GND 7 ISET 8 VDDAT 9 RXP2 10 RXM2 11 TXP2 12 TXM2 13 VDDAT 14 INTR_N 15 VDDC 16 SM3TXEN 17 SM3TXD3 ...
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Pin Number Pin Name 26 SM3RXD2 27 SM3RXD1 28 SM3RXD0 29 SM3CRS 30 GND 31 SM3COL 32 SM4TXEN 33 SM4TXD3 34 SM4TXD2 35 SM4TXD1 36 SM4TXD0 37 SM4TXC/SM4REFCLK 38 VDDIO 39 SM4RXC 40 SM4RXDV/SM4CRSDV January 2011 (1) (2) Type Port ...
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... Port 4 Switch SW4-MII enabled with PHY mode or MAC mode, have to configure SCONF0 pin 48 with SCONF1 Pin 47 Ipd together. See Pin 47 description. LED indicator for Port 2. Ipu/O 2 This pin has to be pulled down by 1K resistor in the design for KSZ8864RMN. 16 Mode 0 Mode 1 Lnk/Act 100Lnk/Act Speed Full duplex Port 4 Switch MAC4 ...
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Pin Number Pin Name 50 P2LED0 51 P1LED1 52 P1LED0 53 MDC 54 MDIO 55 SPIQ 56 SPIC/SCL 57 SPID/SDA 58 SPIS_N January 2011 (1) (2) Type Port Pin Function LED indicator for Port 2. Strap option: Switch MAC3 used ...
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Pin Number Pin Name 59 PS1 60 PS0 61 RST_N 62 VDDC Notes Power supply Input Output. I/O = Bidirectional. Gnd = Ground. Ipu = Input w/internal pull-up. Ipd ...
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... The KSZ8864RMN can function as a managed switch or unmanaged switch EEPROM or micro-controller exists, the KSZ8864RMN will operate from its default setting. The strap-in option pins can be configures by external pull-up/down resistors and take the effect after power up reset or warm reset, the functions are described in the ...
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... Ipd See pin 47 description. LED indicator for Port 2. 2 This pin has to be pulled down by 1K resistor in the design for KSZ8864RMN. LED indicator for Port 2. Strap option: Switch MAC3 used only (default) = Select MII interface for the Switch MAC3 SW3-MII Select RMII interface for the Switch MAC3 SW3-RMII. ...
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Notes Power supply Input Output. I/O = Bidirectional. Gnd = Ground. Ipu = Input w/internal pull-up. Ipd = Input w/internal pull-down. Ipd/O = Input w/internal pull-down during reset, output pin otherwise. Ipu/O = ...
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... The major enhancements of the KSZ8864RMN is small package with configuble of two MII and RMII modes for two MAC interfaces. The KSZ8864RMN supports more new features for host processor management, multiple kind of packets filtering, tag as well as port based VLAN, rapid spanning tree support, IGMP snooping support, port mirroring support and more flexible rate limiting and more functionality ...
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... MDI/MDI-X Auto Crossover To eliminate the need for crossover cables between similar devices, the KSZ8864RMN supports HP Auto MDI/MDI-X and IEEE 802.3u standard MDI/MDI-X auto crossover. HP Auto MDI/MDI-X is the default. The auto-sense function detects remote transmit and receive pairs and correctly assigns transmit and receive pairs for the KSZ8898MQ/TMQ device ...
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Straight Cable A straight cable connects an MDI device to an MDI-X device MDI-X device to an MDI device. The following diagram depicts a typical straight cable connection between a NIC card (MDI) and a switch, or hub ...
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... MDI-X devices). Auto-Negotiation The KSZ8864RMN conforms to the auto-negotiation protocol as described by the 802.3 committee. Auto-negotiation allows unshielded twisted pair (UTP) link partners to select the highest common mode of operation. Link partners advertise their capabilities to each other, and then compare their own capabilities with those they received from their link partners ...
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... If auto-negotiation is not supported or the KSZ8864RMN link partner is forced to bypass auto-negotiation, then the KSZ8864RMN sets its operating mode by observing the signal at its receiver. This is known as parallel detection, and allows the KSZ8864RMN to establish link by listening for a fixed signal protocol in the absence of auto-negotiation advertisement protocol. The auto-negotiation link up process is shown in the following flow chart: January 2011 Figure 3 ...
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... The energy detect mode provides a mechanism to save more power than in the normal operation mode when the KSZ8864RMN is not connected to an active link partner. In this mode, if the cable is not plugged, then the KSZ8864RMN can automatically enter to a low power state, i.e., the energy detect mode. In this mode, KSZ8864RMN will keep transmitting 120ns width pulses at 1 pulse/s rate ...
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... KSZ8864RMN reduces power consumption by disabling all circuitry except the energy detect circuitry of the receiver. The energy detect mode is entered by setting bit [4: register 14. When the KSZ8864RMN is in this mode, it will monitor the cable energy. If there is no energy on the cable for a time longer than pre-configured value at bit [7:0] Go-Sleep time in register 15, then the KSZ8864RMN will go into a low power state ...
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... The KSZ8864RMN features a high-performance switching engine to move data to and from the MAC’s, packet buffers. It operates in store and forward mode, while the efficient switching mechanism reduces overall latency. The KSZ8864RMN has a 64kB internal frame buffer. This resource is shared between all five ports. There are a total of 512 buffers available. Each buffer is sized at 128B. ...
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... The flow control is based on availability of the system resources, including available buffers, available transmit queues and available receive queues. The KSZ8864RMN flow controls a port that has just received a packet if the destination port resource is busy. The KSZ8864RMN issues a flow control frame (XOFF), containing the maximum pause time defined in IEEE standard 802 ...
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Figure 5. Destination Address Resolution Flow Chart – Stage 2 January 2011 31 M9999-012011-1.2 ...
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... Half-Duplex Back Pressure The KSZ8864RMN also provides a half-duplex back pressure option (note: this is not listed in IEEE 802.3 standards). The activation and deactivation conditions are the same as the ones given for full-duplex mode. If back pressure is required, the KSZ8864RMN sends preambles to defer the other station's transmission (carrier sense deference) ...
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... Output Receive data valid Output Receive data bit 3 Output Receive data bit 2 Output Receive data bit 1 Output Receive data bit 0 Output Receive clock 33 KSZ8864RMN MAC Mode Connection External KSZ8864RMN PHY SW3/4-MII Signals MTXEN SMxRXDV MTXD3 SMxRXD[3] MTXD2 SMxRXD[2] MTXD1 SMxRXD[1] MTXD0 ...
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... MTXER would indicate a transmit error from the MAC device. These signals are not appropriate for this configuration. For PHY mode operation, if the device interfacing with the KSZ8864RMN has an MRXER pin, it should be tied low. For MAC mode operation, if the device interfacing with the KSZ8864RMN has an MTXER pin, it should be tied low. ...
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... Switch MAC4 SW4-RMII interface can be used to provide 50MHz clock to opposite RMII from SM4RXC pin with loop back to SM4TXC pin. The SW4-RMII interface can be used to accept 50MHz from external 50MHz clock to SM4TXC when KSZ8864RMN is configured to normal mode by the strap pin P1LED1 pull-down. In the normal mode, the clock source of the KSZ8864RMN comes from the SM4TXC. ...
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... The four priority transmit queues is a new feature in the KSZ8864RMN. The queue 3 is the highest priority queue and Queue 0 is the lowest priority queue. The port registers control 16 bit1 and the port registers control 0 bit0 are used to enable split transmit queues for ports 1and 2, respectively ...
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... PVID can be inserted on the egress port for Ports and 4, respectively. At the egress port, untagged packets are tagged with the ingress port’s default tag. The default tags are programmed in the port registers control 3 and control 4 for ports 1,2,3 and 4, respectively. The KSZ8864RMN will not add tags to already tagged packets. ...
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Blocking state: only packets to the processor are forwarded. Learning is disabled. Port setting: "transmit enable = 0, receive enable = 0, learning disable = 1" Software action: the processor should not send any packets to the port(s) in this ...
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... Bit [7:4] 0,0,0,0 0,0,0,1 0,0,1,0 0,0,1,1 x, 1,x,x 1, x,x,x Egress from Port 4 (KSZ8864RMN Bit [1:0] 0,0 0,1 1,0 1,1 January 2011 Figure 7. Tail Tag Frame Format KSZ8864RMN) Destination Normal (Address Look up for destination) Port 1 (direct forward to port1) ...
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... All the packets received on port A AND transmitted on port B will be mirrored on the sniffer port. To turn on the “AND” feature, set Register 5 bit For example, Port 1 is programmed to be “rx sniff and tx sniff,” and Port 2 is programmed to be the “sniffer port.” A packet, received and transmit on port 1. The KSZ8864RMN will monitor port 1 packets on Port 2. ...
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... PVID” defined in bits [6:5] of the port Register Control 2. These features can be controlled on a port basis. Rate Limiting Support The KSZ8864RMN provides a fine resolution hardware rate limiting. The rate step is 64Kbps when the rate limit is less than 1Mbps rate for 100BT or 10BT. The rate step is 1Mbps when the rate limit is more than 1Mbps rate for 100BT or 10BT (refer to Data Rate Selection Table which follow the end of the Port Register Queue 0− ...
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... The EEPROM should have the entire valid configuration data from Register 0 to Register 255 defined in the “Memory Map,” except the status registers and indirect registers. After reset, the KSZ8864RMN will start to read all control registers sequentially from the EEPROM. The configuration access time (t 30ms, as shown in Figure 12 ...
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... Figure 8. KSZ8864RMN EEPROM Configuration Timing Diagram To configure the KSZ8864RMN with a pre-configured EEPROM use the following steps the board level, connect pin 56 on the KSZ8864RMN to the SCL pin on the EEPROM. Connect pin 57 on the KSZ8864RMN to the SDA pin on the EEPROM. 2. Set the input signals PS[1:0] (pins 59 and 60, respectively) to “00.” This puts the KSZ8864RMN serial bus ...
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... Registers can be read and configuration can be verified with a typical SPI read data cycle as shown in Figure multiple read as shown in Figure 12. Note that read data is registered out of SPIQ on the falling edge of SPIC. 6. After configuration is written and verified, write a ‘1’ to Register 1 bit 0 to begin KSZ8864RMN switch operation. January 2011 Microprocessor Signal Description ...
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January 2011 Figure 11. SPI Multiple Write Figure 12. SPI Multiple Read 45 M9999-012011-1.2 ...
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... The MIIM interface does not have access to all the configuration registers in the KSZ8864RMN. It can only access the standard MIIM registers. See “MIIM Registers”. The SPI interface and MDC/MDIO SMI mode, on the other hand, can be used to access the entire KSZ8864RMN feature set. ...
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... Since the switch configuration registers are 8-bit wide, only the lower 8 bits of Data Bits [15:0] are used. To access the KSZ8864RMN registers 0-255 (0x00 – 0xFF), the following applies: PHYAD [ and REGAD [4:0] are concatenated to form the 8-bit address; that is, {PHYAD [4,3,0], REGAD[4:0]} = bits [7:0] of the 8-bit address. Registers are eight data bits wide. For read operation, data bits [15:8] are read back as 0’ ...
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Register Description Offset Decimal Hex Description 0-1 0x00-0x01 Chip ID Registers 2-13 0x02-0x0D Global Control Registers 14-15 0x0E-0x0F Power Down Management Control Registers 16-20 0x10-0x14 Reserved 21-23 0x15-0x17 Reserved (Factory Test Registers) 24-31 0x18-0x1F Reserved 32-36 0x20-0x24 Port 1 Control ...
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Offset Decimal Hex Description 192-206 0xC0-0xCE Port 1 Control Registers 207 0xCF Reserved (Factory Testing Register) 208-222 0xD0-0xDE Port 2 Control Registers 223 0xDF Reserved (Factory Testing Register) 224-238 0xE0-0xEE Port 3 Control Registers 239 0xEF Reserved (Factory Testing Register) ...
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Global Registers Address Name Register 0 (0x00): Chip ID0 7-0 family ID Register 1 (0x01): Revision ID / Start Switch 7-4 Reserved 3-1 Revision ID 0 Start Switch Register 2 (0x02): Global Control 0 7 New Back-off Enable 6 Reserved ...
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Address Name 4 Flush static MAC table 3 Reserved 2 Reserved 1 UNH Mode 0 Link Change Age Register 3 (0x03): Global Control 1 7 Pass All Frames 6 2K Byte packet support 5 IEEE 802.3x Transmit Flow Control Disable ...
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Address Name 4 IEEE 802.3x Receive Flow Control Disable 3 Frame Length Field Check 2 Aging Enable 1 fast age Enable 0 Aggressive Back Off Enable Register 4 (0x04): Global Control 2 7 Unicast Port-VLAN Mismatch Discard 6 Multicast Storm ...
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Address Name 4 Flow Control and Back Pressure fair Mode 3 No Excessive Collision Drop 2 Huge Packet Support 1 Legal Maximum Packet Size Check Disable 0 Reserved Register 5 (0x05): Global Control 3 7 802.1q VLAN Enable 6 IGMP ...
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Address Name 5 Enable Direct Mode on Switch SW4-MII Interface 4 Enable Pre-Tag on Switch SW4-MII Interface 3-2 Reserved 1 Enable “Tag” Mask 0 Sniff Mode Select Register 6 (0x07): Global Control 4 7 Switch SW4-MII/RMII Back Pressure Enable 6 ...
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Address Name 5 Switch SW4-MII/RMII Flow Control Enable 4 Switch SW4-MII/RMII Speed 3 Null VID Replacement 2-0 Broadcast Storm Protection Rate Bit [10:8] Register 7 (0x07): Global Control 5 7-0 Broadcast Storm Protection Rate Bit [7:0] Register 8 (0x08): Global ...
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Address Name Register 10 (0x0A): Global Control 8 7-0 Factory Testing Register 11 (0x0B): Global Control 9 7 Port 3 SW3-RMII reference clock edge select 6 Port 4 SW4- RMII reference clock edge select 5 Reserved 4 Reserved 3 PHY ...
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Address Name Register 12 (0x0C): Global Control 10 7 Reserved 6 Satus of device with RMII interface at clock mode or normal mode, default is clock mode with 25MHz Crystal clock from pins X1/ CPU interface clock ...
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Address Name 5 PLL Power Down Power Management Mode 2-0 Reserved Register 15 (0x0F): Power Down Management Control Go_sleep_time[7:0] January 2011 Description Pll power down enable Disable 0 = Enable PLL ...
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Port Registers The following registers are used to enable features that are assigned on a per port basis. The register bit assignments are the same for all ports, but the address for each port is different, as indicated. Register 16 ...
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Address Name 0 Two Queues Split Enable January 2011 Description This bit0 in the register16/32/48/64/80 should be combination with Register177/193/209/225/241 bit 1 for port 1-5 will select the split of 1/2/4 queues: For port 1, [Register177 bit 1, Register16 bit ...
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Register 17 (0x11): Reserved Register 33 (0x21): Port 1 Control 1 Register 49 (0x31): Port 2 Control 1 Register 65 (0x41): Port 3 Control 1 Register 81 (0x51): Port 4 Control 1 Address Name 7 Sniffer Port 6 Receive Sniff ...
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Address Name 3 Back Pressure Enable 2 Transmit Enable 1 Receive Enable 0 Learning Disable Note: Bits 2-0 are used for spanning tree support. See “Spanning Tree Support” section. Register 19 (0x13): Reserved Register 35 (0x23): Port 1 Control 3 ...
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Register 87 (0x57): Reserved Control Register Address Name Reserved 3 Port 4 MAC4 SW4-RMII 50MHz clock output disable Reserved Register 25 (0x19): Reserved Register 41 (0x29): Port 1 Status 0 Register 57 (0x39): Port ...
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Register 26 (0x1A): Reserved Register 42 (0x2A): Port 1 PHY Special Control/Status Register 58 (0x3A): Port 2 PHY Special Control/Status Register 74 (0x4A): Reserved Register 90 (0x5A): Reserved Address Name 7-4 Reserved 3 Force_lnk 2 Pwrsave 1 Remote Loopback 0 ...
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Register 28 (0x1C): Reserved Register 44 (0x2C): Port 1 Control 12 Register 60 (0x3C): Port 2 Control 12 Register 76 (0x4C): Reserved Register 92 (0x5C): Reserved Address Name 7 Disable Auto-Negotiation 6 Forced Speed 5 Forced Duplex 4 Advertised Flow ...
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Register 29 (0x1D): Reserved Register 45 (0x2D): Port 1 Control 13 Register 61 (0x3D): Port 2 Control 13 Register 77 (0x4D): Reserved Register 93 (0x5D): Reserved Address Name 7 LED Off 6 Txids 5 Restart AN 4 Reserved 3 Power ...
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Register 30 (0x1E): Reserved Register 46 (0x2E): Port 1 Status 1 Register 62 (0x3E): Port 2 Status 1 Register 78 (0x4E): Reserved Register 94 (0x5E): Reserved Address Name 7 MDIX Status 6 AN Done 5 Link Good 4 Partner Flow ...
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Address Name 5 PHY Isolate 4 Soft Reset 3 Force Link 2-0 Port Operation Mode Indication Note: Port Control 12 and 13, 14 and Port Status 1,2 contents can be accessed by MIIM (MDC/MDIO) interface via the standard MIIM register ...
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Advanced Control Registers Registers 104 to 109 define the switching engine’s MAC address. This 48-bit address is used as the source address in MAC pause control frames. Address Name Register 104 (0x68): MAC Address Register 0 7-0 MACA[47:40] Register 105 ...
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Address Name Register 115 (0x73): Indirect Data Register 5 47-40 Indirect Data Register 116 (0x74): Indirect Data Register 4 39-32 Indirect Data Register 117 (0x75): Indirect Data Register 3 31-24 Indirect Data Register 118 (0x76): Indirect Data Register 2 23-16 ...
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The registers 128, 129 can be used to map from 802.1p priority field 0-7 to switch’s four priority queues 0-3, 0x3 is highest priority queues as priority 3, 0x0 is lowest priority queues as priority 0. Address Name Register 128 ...
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Address Name 4 Reserved Reserved 1 Reserved 0 Reserved Register 131 (0x83): Global Control 15 7 Reserved 6 Reserved 5 Unknown unicast packet forward Unknown unicast packet forward port map Register 132 (0x84): Global ...
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Address Name Register 134 (0x86): Global Control 18 7 Reserved 6 Self Address Filter Enable 5 Unknown IP multicast packet forward Unknown IP multicast packet forward port map Register 135 (0x87): Global Control 19 7 Reserved 6 ...
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Address Name DSCP[5: DSCP[3: DSCP[1:0] Register 145 (0x91): TOS Priority Control Register DSCP[15:14 DSCP[13:12 DSCP[11:10 DSCP[9:8] Register 146 ...
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Address Name Register 150 (0x96): TOS Priority Control Register DSCP[55:54 DSCP[53:52 DSCP[51:50 DSCP[49:48] Register 151 (0x97): TOS Priority Control Register DSCP[63:62 ...
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Address Name Register 157 (0x9D): TOS Priority Control Register DSCP[111:110 DSCP[109:108 DSCP[107:106 DSCP[105:104] Register 158 (0x9E): TOS Priority Control Register DSCP[119:118 ...
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Address Name 1 Insert Source Port PVID for Untagged Packet Destination to Second Lowest Egress Port Note: Enabled by the register 135 bit 2 0 Reserved Register 177 (0xB1): Reserved Register 193 (0xC1): Port 1 Control 9 Register 209 (0xD1): ...
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Address Name Register 179 (0xB3): Reserved Register 195 (0xC3): Port 1 Control 11 Register 211 (0xD3): Port 2 Control 11 Register 227 (0xE3): Port 3 Control 11 Register 243 (0xF3): Port 4 Control 11 7 Enable Port Transmit Queue 2 ...
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Address Name Register 182 (0xB6): Reserved Register 198 (0xC6): Port 1 Rate Limit Control Register 214 (0xD6): Port 2 Rate Limit Control Register 230 (0xE6): Port 3 Rate Limit Control Register 246 (0xF6): Port 4 Rate Limit Control 7 - ...
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Address Name Register 184 (0xB8): Reserved Register 200 (0xC8): Port 1 Priority 1 Ingress Limit Control 2 Register 216 (0xD8): Port 2 Priority 1 Ingress Limit Control 2 Register 232 (0xE8): Port 3 Priority 1 Ingress Limit Control 2 Register ...
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Address Name Register 187 (0xBB): Reserved Register 203 (0xCB): Port 1 Queue 0 Egress Limit Control 1 Register 219 (0xDB): Port 2 Queue 0 Egress Limit Control 1 Register 235 (0xEB): Port 3 Queue 0 Egress Limit Control 1 Register ...
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Address Name Register 190 (0xBE): Reserved Register 206 (0xCE): Port 1 Queue 3 Egress Limit Control 4 Register 222 (0xDE): Port 2 Queue 3 Egress Limit Control 4 Register 238 (0xEE): Port 3 Queue 3 Egress Limit Control 4 Register ...
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Data Rate Selection Table in 10BT Rate for 10BT mode 1 Mbps <= rate <= 9 Mbps rate = 10 Mbps Less than 1Mbps see as below 64 Kbps 128 Kbps 192 Kbps 256 Kbps 320 Kbps 384 Kbps 448 ...
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... N/A Don’t change. N/A Don’t change. N/A Don’t change. N/A Don’t change. N/A Don’t change. KSZ8864RMN N/A Don’t change. N/A Don’t change Invert the phase of SM4TXC clock input in RMII mode, set this bit when connect SW4-RMII clock ...
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... Static MAC Address Table KSZ8864RMN has a static and a dynamic address table. When a DA look-up is requested, both tables will be searched to make a packet forwarding decision. When an SA look-up is requested, only the dynamic table is searched for aging, migration, and learning purposes. The static DA look-up result will have precedence over the dynamic DA look-up result ...
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Address Name 52-48 Forwarding Ports 47-0 MAC Address (DA) January 2011 Description The 5 bits control the forward ports, example: 00001, Reserved 00010, forward to port 1 ….. 10000, forward to port 4 00110, forward to port 1 and port ...
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Examples: (1) Static Address Table Read (read the 2nd entry) Write to Register 110 with 0x10 (read static table selected) Write to Register 111 with 0x1 (trigger the read operation) Then Read Register 113 (63-56) Read Register 114 (55-48) Read ...
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... FID If 802.1q VLAN mode is enabled, KSZ8864RMN assigns a VID to every ingress packet. If the packet is untagged or tagged with a null VID, the packet is assigned with the default port VID of the ingress port. If the packet is tagged with non-null VID, then the VID in the tag is used. The look-up process starts from the VLAN table look-up based on the VID number ...
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Examples: (1) VLAN Table Read (read the VID=2 entry) Write the indirect control and address registers first Write to Register 110 (0x6E) with 0x14 (read VLAN table selected) Write to Register 111 (0x6F) with 0x0 (trigger the read operation for ...
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... Dynamic MAC Address Table This table is read only. The contents are maintained by the KSZ8864RMN only. Address Name Format of Dynamic MAC Address Table (1K entries) 71 MAC Empty 70- Valid Entries 60-59 Time Stamp 58-56 Source Port 55 Data Ready 54-48 FID 47-0 MAC Address Examples: ...
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Dynamic MAC Address Table Read (read the 257 Write to Register 110 with 0x19 (read dynamic table selected) Write to Register 111 with 0x1 (trigger the read operation) and then Read Register 112 (71-64) Read Register 113 (63-56) Read ...
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MIB (Management Information Base) Counters The MIB counters are provided on per port basis. These counters are read using indirect memory access as below: For Port 1 Offset Counter Name 0x20 RxLoPriorityByte 0x21 RxHiPriorityByte 0x22 RxUndersizePkt 0x23 RxFragments 0x24 RxOversize ...
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... All port dropped packet MIB counters do not indicate overflow or validity; therefore the application must keep track of overflow and valid conditions. The KSZ8864RMN provides a total of 34 MIB counter per port. These counter are used to monitor the port detail activity for network management and maintenance. These MIB counters are read using indirect memory access as follows examples ...
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Programming Examples: (1) MIB counter read (read port 1 Rx64Octets counter) Write to Register 110 with 0x1c (read MIB counters selected) Write to Register 111 with 0x2e (trigger the read operation) Then Read Register 117 (counter value 31-24 ...
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... All the registers defined in this section can be also accessed via the SPI interface. Note: different mapping mechanisms used for MIIM and SPI. The “PHYAD” defined in KSZ8864RMN is assigned as “0x2” for port 1, “0x3” for port 2. The “REGAD” supported are 0x0-0x5 (0h-5h), 0x1D (1dh) and 0x1F (1fh). ...
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Address Name 2 Disable far End fault 1 Disable Transmit 0 Disable LED Register 1h: MII Status 15 T4 Capable 14 100 Full Capable 13 100 Half Capable 12 10 Full Capable 11 10 Half Capable 10-7 Reserved 6 Preamble ...
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Address Name 12-11 Reserved 10 Pause 9 Reserved 8 Adv 100 Full 7 Adv 100 Half 6 Adv 10 Full 5 Adv 10 Half 4-0 Selector Field Register 5h: Link Partner Ability 15 Next Page 14 LP ACK 13 Remote ...
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Address Name Register 1fh: PHY Special Control/Status 15-11 Reserved 10-8 Port Operation Mode Indication 7-6 Reserved 5 Polrvs 4 MDI-X status 3 Force_lnk 2 Pwrsave 1 Remote Loopback 0 Reserved January 2011 Description Indicate the current state of port operation ...
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Absolute Maximum Ratings Supply Voltage ( ..................................–0.5V to +2.4V DDAR DDC ( .................................–0.5V to +4.0V DDAT DDIO Input Voltage ........................................–0.5V to +4.0V Output Voltage .....................................–0.5V to +4.0V Lead Temperature (soldering, 10 sec.) ..............270°C Storage ...
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Symbol Parameter TTL Inputs V Input High Voltage IH V Input Low Voltage IL I Input Current (Excluding Pull-up/Pull-down) IN TTL Outputs V Output High Voltage OH V Output Low Voltage OL I Output Tri-State Leakage OZ 100BASE-TX Transmit (measured ...
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Timing Diagrams EEPROM Timing Receive Timin g SCL SDA Figure 13. EEPROM Interface Input Receive Timing Diagram Transmit Timing SCL SDA Figure 14. EEPROM Interface Output Transmit Timing Diagram Symbol Parameter t Clock Cycle CYC1 t Set-Up Time S1 t ...
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MII Timing Figure 15. MAC Mode MII Timing – Data Received from MII Figure 16. MAC Mode MII Timing – Data Transmitted from MII Symbol t CYC3 OV3 January 2011 10Base-T/100Base-TX Parameter Min. Typ. Clock ...
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Figure 18. PHY Mode MII Timing – Data Transmitted from MII January 2011 Figure 17. PHY Mode MII Timing – Data Received from MII Symbol Parameter Min t Clock Cycle CYC4 t Set-Up Time Hold Time 0 ...
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RMII Timing T ran Receive Tim ing REFCLK CRSDV RXD[1:0] Timing Parameter t cyc t 1 ...
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SPI Timing SPIS_N tCHSL SPIC tDVCH SPID SPIQ Symbol Parameter f Clock Frequency C t SPIS_N Inactive Hold Time CHSL t SPIS_N Active Set-Up Time SLCH t SPIS_N Active Hold Time CHSH t SPIS_N Inactive Set-Up Time SHCH t SPIS_N ...
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Symbol Parameter f Clock Frequency C t SPIQ Hold Time CLQX t Clock Low to SPIQ Valid CLQV t Clock High Time CH t Clock Low Time CL t SPIQ Rise Time QLQH t SPIQ fall Time QHQL t SPIQ ...
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Auto-Negotiation Timing Symbol Parameter t FLP burst to FLP burst BTB t FLP burst width FLPW t Clock/Data pulse width PW t Clock pulse to Data pulse CTD t Clock pulse to Clock pulse CTC Number of Clock/Data pulse per ...
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MDC/MDIO Timing Timing Parameter Description t MDC period P t MDIO (PHY input) setup to rising edge of MDC 1MD1 t MDIO (PHY input) hold from rising edge of MDC MD2 t MDIO (PHY output) delay from rising edge of ...
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Reset Timing Symbol Parameter t Stable Supply Voltages to Reset High SR t Configuration Set-Up Time CS t Configuration Hold Time CH t Reset to Strap-In Pin Output RC tvr 3.3V rise time January 2011 Figure 25. Reset Timing Table ...
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Reset Circuit Diagram Micrel recommends the following discrete reset circuit, as shown in Figure 26, when powering up the KS8895MQ device. For the application where the reset circuit signal comes from another device (e.g., CPU, FPGA, etc), Micrel recommends the ...
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Selection of Isolation Transformer One simple 1:1 isolation transformer is needed at the line interface. An isolation transformer with integrated common- mode choke is recommended for exceeding FCC requirements at line side. Request to separate the center taps of RX/TX ...
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Package Information MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this ...